ivybridge native gfx init: Adjust state to be compatible with OPROM.

My main payload is GRUB and I load SeaBIOS as secondary payload when for some
reason I want to boot windows. In this scenario SeaBIOS runs VGA oprom
(SeaVGABIOS is not good enough with intel gfx). VGA oprom expects either
completely uninited gfx or some special state in gmbus and software scratch
registers. Provide this state.

The only alternative without this patch for such usecase is to use oprom and
I'd like to avoid doing so when going my main boot path to GNU/Linux.

Change-Id: I38e78fb845e43b81df084cd4d65f4618bfb2506d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10205
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

3 files changed, 34 insertions, 2 deletions

diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c
index e70156eb28..052f099177 100644
--- a/src/drivers/intel/gma/edid.c
+++ b/src/drivers/intel/gma/edid.c
@@ -37,6 +37,30 @@ static void wait_rdy(u8 *mmio)
 	}
 }
 
+static void intel_gmbus_stop_bus(u8 * mmio, u8 bus)
+{
+	wait_rdy(mmio);
+	write32(mmio + 4 * 0, bus);
+	wait_rdy(mmio);
+	write32(mmio + 4 * 8, 0);
+	write32(mmio + 4 * 1, 0x4e0400a1);
+	wait_rdy(mmio);
+	write32(mmio + 4 * 8, 0);
+	write32(mmio + 4 * 1, 0x80000000);
+	write32(mmio + 4 * 1, 0x00000000);
+	wait_rdy(mmio);
+	write32(mmio + 4 * 1, 0x480000a0);
+	wait_rdy(mmio);
+	write32(mmio + 4 * 0, 0x48000000);
+	write32(mmio + 4 * 2, 0x00008000);
+}
+
+void intel_gmbus_stop(u8 *mmio)
+{
+	intel_gmbus_stop_bus(mmio, 6);
+	intel_gmbus_stop_bus(mmio, 2);
+}
+
 void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
 {
 	int i;
diff --git a/src/drivers/intel/gma/edid.h b/src/drivers/intel/gma/edid.h
index c4763919bd..d8214cf329 100644
--- a/src/drivers/intel/gma/edid.h
+++ b/src/drivers/intel/gma/edid.h
@@ -1 +1,2 @@
 void intel_gmbus_read_edid(u8 *gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size);
+void intel_gmbus_stop(u8 *gmbus_mmio);
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index 6c1295a73b..8fa780f5e8 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -206,6 +206,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	enable_port(mmio);
 
 	intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128);
+	intel_gmbus_stop(mmio + PCH_GMBUS0);
 	decode_edid(edid_data,
 		    sizeof(edid_data), &edid);
 
@@ -236,9 +237,8 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	u32 pixel_m1 = 1;
 	u32 pixel_m2 = 1;
 
-#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
 	vga_textmode_init();
-#else
+#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
 	vga_sr_write(1, 1);
 	vga_sr_write(0x2, 0xf);
 	vga_sr_write(0x3, 0x0);
@@ -513,6 +513,13 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	set_vbe_mode_info_valid(&edid, lfb);
 #endif
 
+	/* Doesn't change any hw behaviour but vga oprom expects it there. */
+	write32(mmio + 0x0004f040, 0x01000008);
+	write32(mmio + 0x0004f044, 0x00001800);
+	write32(mmio + 0x0004f04c, 0x7f7f0000);
+	write32(mmio + 0x0004f054, 0x0000422d);
+	write32(mmio + 0x0004f05c, 0x00000008);
+
 	/* Linux relies on VBT for panel info.  */
 	generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
 				  "$VBT SNB/IVB-MOBILE ");