/mb/google/hatch: Create jinlon variant

Create new variant for jinlon

BUG=b:144150654
TEST=emerge-hatch coreboot chromeos-bootimage and boot on jinlon proto
board

Change-Id: I8deb29041475e38cbbf2f54519940f62b9f21822
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36681
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 367 insertions, 0 deletions

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 6c0a94afe6..943ec612a4 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -92,6 +92,7 @@ config MAINBOARD_PART_NUMBER
 	default "Hatch" if BOARD_GOOGLE_HATCH
 	default "Helios" if BOARD_GOOGLE_HELIOS
 	default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP
+	default "Jinlon" if BOARD_GOOGLE_JINLON
 	default "Kindred" if BOARD_GOOGLE_KINDRED
 	default "Kohaku" if BOARD_GOOGLE_KOHAKU
 	default "Puff" if BOARD_GOOGLE_PUFF
@@ -120,6 +121,7 @@ config VARIANT_DIR
 	default "hatch" if BOARD_GOOGLE_HATCH
 	default "helios" if BOARD_GOOGLE_HELIOS
 	default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP
+	default "jinlon" if BOARD_GOOGLE_JINLON
 	default "kindred" if BOARD_GOOGLE_KINDRED
 	default "kohaku" if BOARD_GOOGLE_KOHAKU
 	default "puff" if BOARD_GOOGLE_PUFF
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name
index ec12096269..82da88324c 100644
--- a/src/mainboard/google/hatch/Kconfig.name
+++ b/src/mainboard/google/hatch/Kconfig.name
@@ -15,6 +15,11 @@ config BOARD_GOOGLE_HATCH
 	select BOARD_GOOGLE_BASEBOARD_HATCH
 	select BOARD_ROMSIZE_KB_32768
 
+config BOARD_GOOGLE_JINLON
+	bool "-> Jinlon"
+	select BOARD_GOOGLE_BASEBOARD_HATCH
+	select BOARD_ROMSIZE_KB_16384
+
 config BOARD_GOOGLE_KOHAKU
 	bool "->  Kohaku"
 	select BOARD_GOOGLE_BASEBOARD_HATCH
diff --git a/src/mainboard/google/hatch/variants/jinlon/Makefile.inc b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc
new file mode 100644
index 0000000000..6e5d8835db
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/jinlon/Makefile.inc
@@ -0,0 +1,27 @@
+## This file is part of the coreboot project.
+##
+## Copyright 2019 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_SOURCES = 4G_2400         # 0b000
+SPD_SOURCES += empty_ddr4     # 0b001
+SPD_SOURCES += 8G_2400        # 0b010
+SPD_SOURCES += 8G_2666        # 0b011
+SPD_SOURCES += 16G_2400       # 0b100
+SPD_SOURCES += 16G_2666       # 0b101
+SPD_SOURCES += 8G_3200        # 0b110
+SPD_SOURCES += 16G_3200       # 0b111
+SPD_SOURCES += 16G_2666_2bg   # 0b1000
+SPD_SOURCES += 16G_3200_4bg   # 0b1001
+
+bootblock-y += gpio.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c
new file mode 100644
index 0000000000..7e475fa6a2
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+static const struct pad_config gpio_table[] = {
+	/* A0  : NC */
+	PAD_NC(GPP_A0, NONE),
+	/* A6  : NC */
+	PAD_NC(GPP_A6, NONE),
+	/* A8  : NC */
+	PAD_NC(GPP_A8, NONE),
+	/* A10 : NC */
+	PAD_NC(GPP_A10, NONE),
+	/* C12 : FPMCU_PCH_BOOT1 */
+	PAD_CFG_GPO(GPP_C12, 0, DEEP),
+	/* F1  : NC */
+	PAD_NC(GPP_F1, NONE),
+	/* F3  : MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
+	/* F10 : MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
+	/* F11 : EMMC_CMD ==> NC */
+	PAD_NC(GPP_F11, NONE),
+	/* F12 : EMMC_DATA0 ==> NC */
+	PAD_NC(GPP_F12, NONE),
+	/* F13 : EMMC_DATA1 ==> NC */
+	PAD_NC(GPP_F13, NONE),
+	/* F14 : EMMC_DATA2 ==> NC */
+	PAD_NC(GPP_F14, NONE),
+	/* F15 : EMMC_DATA3 ==> NC */
+	PAD_NC(GPP_F15, NONE),
+	/* F16 : EMMC_DATA4 ==> NC */
+	PAD_NC(GPP_F16, NONE),
+	/* F17 : EMMC_DATA5 ==> NC */
+	PAD_NC(GPP_F17, NONE),
+	/* F18 : EMMC_DATA6 ==> NC */
+	PAD_NC(GPP_F18, NONE),
+	/* F19 : EMMC_DATA7 ==> NC */
+	PAD_NC(GPP_F19, NONE),
+	/* F20 : EMMC_RCLK ==> NC */
+	PAD_NC(GPP_F20, NONE),
+	/* F21 : EMMC_CLK ==> NC */
+	PAD_NC(GPP_F21, NONE),
+	/* F22 : EMMC_RESET# ==> NC */
+	PAD_NC(GPP_F22, NONE),
+	/* H19 : MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
+	/* H22 : MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
+};
+
+const struct pad_config *override_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+/*
+ * GPIOs configured before ramstage
+ * Note: the Hatch platform's romstage will configure
+ * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
+ * as inputs before it reads them, so they are not
+ * needed in this table.
+ */
+static const struct pad_config early_gpio_table[] = {
+	/* B15 : H1_SLAVE_SPI_CS_L */
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+	/* B16 : H1_SLAVE_SPI_CLK */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+	/* B17 : H1_SLAVE_SPI_MISO_R */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+	/* B18 : H1_SLAVE_SPI_MOSI_R */
+	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C14 : BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_C14, 0, DEEP),
+	/* PCH_WP_OD */
+	PAD_CFG_GPI(GPP_C20, NONE, DEEP),
+	/* C21 : H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+	/* C23 : WLAN_PE_RST# */
+	PAD_CFG_GPO(GPP_C23, 1, DEEP),
+	/* E1  : M2_SSD_PEDET */
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
+	/* E5  : SATA_DEVSLP1 */
+	PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
+	/* F2  : MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000000..f1f09438fa
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h
new file mode 100644
index 0000000000..768987d225
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h
new file mode 100644
index 0000000000..92f9d412fd
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/gpio.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0	GPP_H19
+#define GPIO_MEM_CONFIG_1	GPP_H22
+#define GPIO_MEM_CONFIG_2	GPP_F10
+#define GPIO_MEM_CONFIG_3	GPP_F3
+
+#endif
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
new file mode 100644
index 0000000000..28b18b8b7f
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
@@ -0,0 +1,159 @@
+chip soc/intel/cannonlake
+
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0] = PchSerialIoPci,
+		[PchSerialIoIndexI2C1] = PchSerialIoPci,
+		[PchSerialIoIndexI2C2] = PchSerialIoPci,
+		[PchSerialIoIndexI2C3] = PchSerialIoPci,
+		[PchSerialIoIndexI2C4] = PchSerialIoPci,
+		[PchSerialIoIndexI2C5] = PchSerialIoPci,
+		[PchSerialIoIndexSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI0             | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#|                   | before memory is up       |
+	#| GSPI1             | FP MCU                    |
+	#| I2C0              | Touchpad                  |
+	#| I2C1              | Touch screen              |
+	#| I2C4              | Audio                     |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "vSD3_CD_B"
+
+	# Enable eMMC HS400
+	register "ScsEmmcHs400Enabled" = "1"
+
+	device domain 0 on
+		device pci 15.0 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
+				register "wake" = "GPE0_DW0_21"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end # I2C #0
+		device pci 15.1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GTCH7503""
+				register "generic.desc" = ""G2TOUCH Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+				register "generic.reset_delay_ms" = "50"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.disable_gpio_export_in_crs" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 40 on end
+			end
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+				register "probed" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+				register "reset_delay_ms" = "100"
+				register "reset_off_delay_ms" = "5"
+				register "has_power_resource" = "1"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
+				register "enable_delay_ms" = "10"
+				register "enable_off_delay_ms" = "1"
+				device i2c 10 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GDIX0000""
+				register "generic.desc" = ""Goodix Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+				register "generic.reset_delay_ms" = "120"
+				register "generic.reset_off_delay_ms" = "3"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
+				register "generic.enable_delay_ms" = "10"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_off_delay_ms" = "20"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 5d on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN2513""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
+				register "generic.enable_delay_ms" = "10"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
+				register "generic.stop_delay_ms" = "130"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+		end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 19.0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Realtek RT5682""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
+				register "property_count" = "1"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+		end #I2C #4
+		device pci 1a.0 on  end # eMMC
+		device pci 1e.3 on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)"
+				register "wake" = "GPE0_DW0_23"
+				device spi 1 on end
+			end # FPMCU
+		end # GSPI #1
+	end
+
+end