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authorJohn Zhao <john.zhao@intel.com>2020-05-19 20:21:00 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:07:21 +0000
commit3c8cb24fc32d0322da5cfd7fabae3b66ac16470b (patch)
tree76344fe3d349609ae54f3e435eddc1f96a414926 /src
parent8aac881fe8caacd264fe6e0951750c6357bb3b5c (diff)
downloadcoreboot-3c8cb24fc32d0322da5cfd7fabae3b66ac16470b.tar.xz
mb/intel/tglrvp: Enable D3HotEnable and D3ColdEnable for tglrvp
This explicitly enables both of TCSS D3HotEnable and D3ColdEnable from tglrvp devicetree.cb setting. BUG=:b:146624360 TEST=Built and booted on tglrvp. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I3b77fe15bd67e513f193f704030a98241e058437 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb4
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb4
2 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 045dc89e4d..24cc907da7 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -109,6 +109,10 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoPci,
}"
+ # D3Hot and D3Cold for TCSS
+ register "TcssD3HotEnable" = "1"
+ register "TcssD3ColdEnable" = "1"
+
# TCSS USB3
register "TcssAuxOri" = "0"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 83b6c0ae0c..eb6814e5bf 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -105,6 +105,10 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoPci,
}"
+ # D3Hot and D3Cold for TCSS
+ register "TcssD3HotEnable" = "1"
+ register "TcssD3ColdEnable" = "1"
+
# TCSS USB3
register "TcssAuxOri" = "0"