mainboard/asus/am1i-a: add support for board ASUS AM1I-A

Add code to support the board ASUS AM1I-A. Tested with multiple payloads
and OSes with satisfactory results. S3 suspend/resume works fine with
Linux but has issues with Windows (an exception is thrown). However,
after manually rebooting, Windows resumes the suspended session.

* Tested with: SeaBIOS 1.11 + Linux 4.10 - OK
* Tested with: tianocore vEDK2017 + MS Windows 8.1 - OK
* Tested with: FILO 0.6.0 - hangs after showing the banner

Details are going to be published on the board's status page.

Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/23002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

23 files changed, 2122 insertions, 0 deletions

diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c
new file mode 100644
index 0000000000..dae44ca792
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c
@@ -0,0 +1,150 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
+ * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia.h>
+#include "AGESA.h"
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
+#include "FchPlatform.h"
+#include "cbfs.h"
+#include <stdlib.h>
+#include <pc80/mc146818rtc.h>
+#include <types.h>
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+	{AGESA_DO_RESET,                 agesa_Reset },
+	{AGESA_READ_SPD,                 agesa_ReadSpd },
+	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
+	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
+	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
+	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/**
+ * CODEC Initialization Table for Azalia HD Audio using Realtek ALC887-VD chip (from linux, running under vendor bios)
+ */
+const CODEC_ENTRY Alc887_VerbTbl[] =
+{
+	{ 0x11, 0x40330000 },
+	{ 0x12, 0x411111f0 },
+	{ 0x14, 0x01014010 },
+	{ 0x15, 0x411111f0 },
+	{ 0x16, 0x411111f0 },
+	{ 0x17, 0x411111f0 },
+	{ 0x18, 0x01a19030 },
+	{ 0x19, 0x02a19040 },
+	{ 0x1a, 0x0181303f },
+	{ 0x1b, 0x02214020 },
+	{ 0x1c, 0x411111f0 },
+	{ 0x1d, 0x4024c601 },
+	{ 0x1e, 0x411111f0 },
+	{ 0x1f, 0x411111f0 }
+};
+
+static const CODEC_TBL_LIST CodecTableList[] =
+{
+	{0x10ec0887, (CODEC_ENTRY*)&Alc887_VerbTbl[0]},
+	{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
+#define FAN_INPUT_INTERNAL_DIODE	0
+#define FAN_INPUT_TEMP0			1
+#define FAN_INPUT_TEMP1			2
+#define FAN_INPUT_TEMP2			3
+#define FAN_INPUT_TEMP3			4
+#define FAN_INPUT_TEMP0_FILTER		5
+#define FAN_INPUT_ZERO			6
+#define FAN_INPUT_DISABLED		7
+
+#define FAN_AUTOMODE			(1 << 0)
+#define FAN_LINEARMODE			(1 << 1)
+#define FAN_STEPMODE			~(1 << 1)
+#define FAN_POLARITY_HIGH		(1 << 2)
+#define FAN_POLARITY_LOW		~(1 << 2)
+
+/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
+#define FREQ_28KHZ			0x0
+#define FREQ_25KHZ			0x1
+#define FREQ_23KHZ			0x2
+#define FREQ_21KHZ			0x3
+#define FREQ_29KHZ			0x4
+#define FREQ_18KHZ			0x5
+#define FREQ_100HZ			0xF7
+#define FREQ_87HZ			0xF8
+#define FREQ_58HZ			0xF9
+#define FREQ_44HZ			0xFA
+#define FREQ_35HZ			0xFB
+#define FREQ_29HZ			0xFC
+#define FREQ_22HZ			0xFD
+#define FREQ_14HZ			0xFE
+#define FREQ_11HZ			0xFF
+
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
+{
+	FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+	FchParams_reset->Mode = 6;
+
+	/* Read SATA speed setting from CMOS */
+	enum cb_err ret;
+	ret = get_option(&FchParams_reset->SataSetMaxGen2, "sata_speed");
+	if  (ret != CB_SUCCESS) {
+		FchParams_reset->SataSetMaxGen2 = 0;
+		printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret);
+	}
+	printk(BIOS_DEBUG, "Force SATA 3Gbps mode = %x\n", FchParams_reset->SataSetMaxGen2);
+}
+
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
+{
+	/* Azalia Controller OEM Codec Table Pointer */
+	FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
+
+	/* Fan Control */
+	FchParams_env->Imc.ImcEnable = FALSE;
+	FchParams_env->Hwm.HwMonitorEnable = FALSE;
+	FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
+
+	/* Read SATA controller mode from CMOS */
+	enum cb_err ret;
+	ret = get_option(&FchParams_env->Sata.SataClass, "sata_mode");
+	if ( ret != CB_SUCCESS) {
+		FchParams_env->Sata.SataClass = 0;
+		printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret);
+	}
+
+	// code from olivehillplus (ft3b) - only place where sata is configured
+	switch ((SATA_CLASS)FchParams_env->Sata.SataClass) {
+	case SataLegacyIde:
+	case SataRaid:
+	case SataAhci:
+	case SataAhci7804:
+		FchParams_env->Sata.SataIdeMode = FALSE;
+		printk(BIOS_DEBUG, "AHCI or RAID or IDE = %x\n", FchParams_env->Sata.SataClass);
+		break;
+
+	case SataIde2Ahci:
+	case SataIde2Ahci7804:
+	default: /* SataNativeIde */
+		FchParams_env->Sata.SataIdeMode = TRUE;
+		printk(BIOS_DEBUG, "IDE2AHCI = %x\n", FchParams_env->Sata.SataClass);
+		break;
+	}
+}
diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig
new file mode 100644
index 0000000000..e0a78ff1ad
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/Kconfig
@@ -0,0 +1,60 @@
+if BOARD_ASUS_AM1I_A
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select CPU_AMD_AGESA_FAMILY16_KB
+	select FORCE_AM1_SOCKET_SUPPORT
+	select GFXUMA
+	select HAVE_OPTION_TABLE
+	select USE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
+	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+	select SUPERIO_ITE_IT8623E
+
+config MAINBOARD_DIR
+	string
+	default asus/am1i-a
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "AM1I-A"
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x200000
+
+config MAX_CPUS
+	int
+	default 4
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+
+config IRQ_SLOT_COUNT
+	int
+	default 9
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config VGA_BIOS_ID
+	string
+	default "1002,9836"
+
+config HUDSON_LEGACY_FREE
+	bool
+	default n
+
+config HUDSON_IMC_FWM
+	bool
+	default n
+
+endif # BOARD_ASUS_AM1I_A
diff --git a/src/mainboard/asus/am1i-a/Kconfig.name b/src/mainboard/asus/am1i-a/Kconfig.name
new file mode 100644
index 0000000000..840e821f65
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_AM1I_A
+	bool "AM1I-A"
diff --git a/src/mainboard/asus/am1i-a/Makefile.inc b/src/mainboard/asus/am1i-a/Makefile.inc
new file mode 100644
index 0000000000..f8895faa92
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+romstage-y += buildOpts.c
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+
+ramstage-y += buildOpts.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asus/am1i-a/OemCustomize.c b/src/mainboard/asus/am1i-a/OemCustomize.c
new file mode 100644
index 0000000000..f339ffcabb
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/OemCustomize.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "AGESA.h"
+#include <PlatformMemoryConfiguration.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x01, 0)
+	},
+	/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x02, 0)
+	},
+	/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x03, 0)
+	},
+	/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x04, 0)
+	},
+	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0x05, 0)
+	}
+};
+
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	/* DP0 to HDMI */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
+	},
+	/* DP1 to DVI-D */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeSingleLinkDVI, Aux2, Hdp2)
+	},
+	/* DP2 to VGA */
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3)
+	},
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList
+};
+
+
+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+	FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
+
+	FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+	FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+
+	FchReset->SataEnable = 1;
+	FchReset->IdeEnable = 0;
+}
+
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+}
+
+/*----------------------------------------------------------------------------------------
+ *                        CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ *  use its default conservative settings.
+ */
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
+	#define SEED_A 0x12
+	HW_RXEN_SEED(
+		ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+		SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+		SEED_A),
+
+  NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
+  NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
+  MOTHER_BOARD_LAYERS(LAYERS_4),
+
+  MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+  CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
+  ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
+  CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+
+  PSO_END
+};
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
+{
+	/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+	InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/asus/am1i-a/OptionsIds.h b/src/mainboard/asus/am1i-a/OptionsIds.h
new file mode 100644
index 0000000000..eaf2442651
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/OptionsIds.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ *  This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ *    IDSOPT_IDS_ENABLED
+ *    IDSOPT_ERROR_TRAP_ENABLED
+ *    IDSOPT_CONTROL_ENABLED
+ *    IDSOPT_TRACING_ENABLED
+ *    IDSOPT_PERF_ANALYSIS
+ *    IDSOPT_ASSERT_ENABLED
+ *    IDS_DEBUG_PORT
+ *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+#define IDSOPT_IDS_ENABLED     TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS   TRUE
+#define IDSOPT_ASSERT_ENABLED  TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED  FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW    FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT       FALSE
+//#define IDS_DEBUG_PORT    0x80
+
+#endif
diff --git a/src/mainboard/asus/am1i-a/acpi/mainboard.asl b/src/mainboard/asus/am1i-a/acpi/mainboard.asl
new file mode 100644
index 0000000000..68609d868e
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/mainboard.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Memory related values */
+Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0)	/* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+/* Some global data */
+Name(OSVR, 3)	/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones)	/* Assume nothing */
+Name(PMOD, One)	/* Assume APIC */
+
+/* AcpiGpe0Blk */
+OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
+	Field(GP0B, ByteAcc, NoLock, Preserve) {
+	, 11,
+	USBS, 1,
+}
diff --git a/src/mainboard/asus/am1i-a/acpi/routing.asl b/src/mainboard/asus/am1i-a/acpi/routing.asl
new file mode 100644
index 0000000000..76d1c47344
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/routing.asl
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Routing is in System Bus scope */
+Name(PR0, Package(){
+	/* NB devices */
+	/* Bus 0, Dev 0 - F16 Host Controller */
+
+	/* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */
+	/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+	Package(){0x0001FFFF, 0, INTA, 0 },
+	Package(){0x0001FFFF, 1, INTB, 0 },
+
+	/* Bus 0, Dev 2 - PCIe Bridges */
+	Package(){0x0002FFFF, 0, INTA, 0 },
+	Package(){0x0002FFFF, 1, INTB, 0 },
+	Package(){0x0002FFFF, 2, INTC, 0 },
+	Package(){0x0002FFFF, 3, INTD, 0 },
+
+	/* FCH devices */
+	/* Bus 0, Dev 14 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+	Package(){0x0014FFFF, 0, INTA, 0 },
+	Package(){0x0014FFFF, 1, INTB, 0 },
+	Package(){0x0014FFFF, 2, INTC, 0 },
+	Package(){0x0014FFFF, 3, INTD, 0 },
+
+	/* Bus 0, Dev 12 Func 0 - USB: OHCI */
+	/* Bus 0, Dev 12 Func 2 - USB: EHCI */
+	Package(){0x0012FFFF, 0, INTC, 0 },
+	Package(){0x0012FFFF, 1, INTB, 0 },
+
+	/* Bus 0, Dev 13 Func 0 - USB: OHCI */
+	/* Bus 0, Dev 13 Func 2 - USB: EHCI */
+	Package(){0x0013FFFF, 0, INTC, 0 },
+	Package(){0x0013FFFF, 1, INTB, 0 },
+
+	/* Bus 0, Dev 10 Func 0 - USB: XHCI */
+	Package(){0x0010FFFF, 0, INTC, 0 },
+
+	/* Bus 0, Dev 11 - SATA controller */
+	Package(){0x0011FFFF, 0, INTD, 0 },
+})
+
+Name(APR0, Package(){
+	/* NB devices in APIC mode */
+	/* Bus 0, Dev 0 - F16 Host Controller */
+
+	/* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */
+	/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
+	Package(){0x0001FFFF, 0, 0, 16 },
+	Package(){0x0001FFFF, 1, 0, 17 },
+
+	/* Bus 0, Dev 2 - PCIe Bridges  */
+	Package(){0x0002FFFF, 0, 0, 16 },
+	Package(){0x0002FFFF, 1, 0, 17 },
+	Package(){0x0002FFFF, 2, 0, 18 },
+	Package(){0x0002FFFF, 3, 0, 19 },
+
+	/* SB devices in APIC mode */
+	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
+	Package(){0x0014FFFF, 0, 0, 16 },
+	Package(){0x0014FFFF, 1, 0, 17 },
+	Package(){0x0014FFFF, 2, 0, 18 },
+	Package(){0x0014FFFF, 3, 0, 19 },
+
+	/* Bus 0, Dev 12 Func 0 - USB: OHCI */
+	/* Bus 0, Dev 12 Func 1 - USB: EHCI */
+	Package(){0x0012FFFF, 0, 0, 18 },
+	Package(){0x0012FFFF, 1, 0, 17 },
+
+	/* Bus 0, Dev 13 Func 0 - USB: OHCI */
+	/* Bus 0, Dev 13 Func 1 - USB: EHCI */
+	Package(){0x0013FFFF, 0, 0, 18 },
+	Package(){0x0013FFFF, 1, 0, 17 },
+
+	/* Bus 0, Dev 10, Func 0 - USB: XHCI */
+	Package(){0x0010FFFF, 0, 0, 18 },
+
+	/* Bus 0, Dev 11 - SATA controller */
+	Package(){0x0011FFFF, 0, 0, 19 },
+})
+
+/* GPP 0 - PCIe 4x slot */
+Name(PS4, Package(){
+	Package(){0x0000FFFF, 0, INTA, 0 },
+	Package(){0x0000FFFF, 1, INTB, 0 },
+	Package(){0x0000FFFF, 2, INTC, 0 },
+	Package(){0x0000FFFF, 3, INTD, 0 },
+})
+Name(APS4, Package(){
+	Package(){0x0000FFFF, 0, 0, 16 },
+	Package(){0x0000FFFF, 1, 0, 17 },
+	Package(){0x0000FFFF, 2, 0, 18 },
+	Package(){0x0000FFFF, 3, 0, 19 },
+})
+
+/* GPP 1 - not used */
+Name(PS5, Package(){
+	Package(){0x0000FFFF, 0, INTB, 0 },
+	Package(){0x0000FFFF, 1, INTC, 0 },
+	Package(){0x0000FFFF, 2, INTD, 0 },
+	Package(){0x0000FFFF, 3, INTA, 0 },
+})
+Name(APS5, Package(){
+	Package(){0x0000FFFF, 0, 0, 28 },
+	Package(){0x0000FFFF, 1, 0, 29 },
+	Package(){0x0000FFFF, 2, 0, 30 },
+	Package(){0x0000FFFF, 3, 0, 31 },
+})
+
+/* GPP 2 - not used */
+Name(PS6, Package(){
+	Package(){0x0000FFFF, 0, INTC, 0 },
+	Package(){0x0000FFFF, 1, INTD, 0 },
+	Package(){0x0000FFFF, 2, INTA, 0 },
+	Package(){0x0000FFFF, 3, INTB, 0 },
+})
+Name(APS6, Package(){
+	Package(){0x0000FFFF, 0, 0, 32 },
+	Package(){0x0000FFFF, 1, 0, 33 },
+	Package(){0x0000FFFF, 2, 0, 34 },
+	Package(){0x0000FFFF, 3, 0, 35 },
+})
+
+/* GPP 3 - not used */
+Name(PS7, Package(){
+	Package(){0x0000FFFF, 0, INTD, 0 },
+	Package(){0x0000FFFF, 1, INTA, 0 },
+	Package(){0x0000FFFF, 2, INTB, 0 },
+	Package(){0x0000FFFF, 3, INTC, 0 },
+})
+Name(APS7, Package(){
+	Package(){0x0000FFFF, 0, 0, 36 },
+	Package(){0x0000FFFF, 1, 0, 37 },
+	Package(){0x0000FFFF, 2, 0, 38 },
+	Package(){0x0000FFFF, 3, 0, 39 },
+})
+
+/* GPP 4 - Realtek GBE */
+Name(PS8, Package(){
+	Package(){0x0000FFFF, 0, INTB, 0 },
+	Package(){0x0000FFFF, 1, INTC, 0 },
+	Package(){0x0000FFFF, 2, INTD, 0 },
+	Package(){0x0000FFFF, 3, INTA, 0 },
+})
+Name(APS8, Package(){
+	Package(){0x0000FFFF, 0, 0, 17 },
+	Package(){0x0000FFFF, 1, 0, 18 },
+	Package(){0x0000FFFF, 2, 0, 19 },
+	Package(){0x0000FFFF, 3, 0, 16 },
+})
diff --git a/src/mainboard/asus/am1i-a/acpi/sata.asl b/src/mainboard/asus/am1i-a/acpi/sata.asl
new file mode 100644
index 0000000000..9349be71e6
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/sata.asl
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012-2013 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}
diff --git a/src/mainboard/asus/am1i-a/acpi/si.asl b/src/mainboard/asus/am1i-a/acpi/si.asl
new file mode 100644
index 0000000000..292347127e
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/si.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_SI) {
+	Method(_SST, 1) {
+		/* DBGO("\\_SI\\_SST\n") */
+		/* DBGO("   New Indicator state: ") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+	}
+} /* End Scope SI */
diff --git a/src/mainboard/asus/am1i-a/acpi/sleep.asl b/src/mainboard/asus/am1i-a/acpi/sleep.asl
new file mode 100644
index 0000000000..1225a62785
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/sleep.asl
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+*		-none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method.  This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver.  This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+
+External(\_SB.APTS, MethodObj)
+External(\_SB.AWAK, MethodObj)
+
+Method(_PTS, 1) {
+	/* DBGO("\\_PTS\n") */
+	/* DBGO("From S0 to S") */
+	/* DBGO(Arg0) */
+	/* DBGO("\n") */
+
+	/* Clear wake status structure. */
+	Store(0, Index(WKST,0))
+	Store(0, Index(WKST,1))
+	Store(7, UPWS)
+	\_SB.APTS(Arg0)
+} /* End Method(\_PTS) */
+
+/*
+*	\_BFS OEM Back From Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		-none-
+*/
+Method(\_BFS, 1) {
+	/* DBGO("\\_BFS\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+}
+
+/*
+*  \_WAK System Wake method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		Return package of 2 DWords
+*		Dword 1 - Status
+*			0x00000000	wake succeeded
+*			0x00000001	Wake was signaled but failed due to lack of power
+*			0x00000002	Wake was signaled but failed due to thermal condition
+*		Dword 2 - Power Supply state
+*			if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+	/* DBGO("\\_WAK\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+	Store(1,USBS)
+
+	\_SB.AWAK(Arg0)
+
+	Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/am1i-a/acpi/superio.asl b/src/mainboard/asus/am1i-a/acpi/superio.asl
new file mode 100644
index 0000000000..6ff5b7fc09
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi/superio.asl
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
+ * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+// Values, defined here, must match settings in devicetree.cb
+
+Device (PS2M) {
+	Name (_HID, EisaId ("PNP0F13"))
+	Name (_CRS, ResourceTemplate () {
+		IRQNoFlags () {12}
+	})
+}
+
+Device (PS2K) {
+	Name (_HID, EisaId ("PNP0303"))
+	Name (_CRS, ResourceTemplate () {
+		IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
+		IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
+		IRQNoFlags () {1}
+	})
+}
+
+Device (COM1) {
+	Name (_HID, EISAID ("PNP0501"))
+	Name (_UID, 1)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+		IRQNoFlags () {4}
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+		IRQNoFlags () {4}
+	})
+}
+
+Device (COM2) {
+	Name (_HID, EISAID ("PNP0501"))
+	Name (_UID, 2)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
+		IRQNoFlags () {3}
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
+		IRQNoFlags () {3}
+	})
+}
+
+Device (LPT1) {
+	Name (_HID, EISAID ("PNP0401"))
+	Name (_UID, 1)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0378, 0x0378, 0x04, 0x08)
+		IO (Decode16, 0x0778, 0x0778, 0x04, 0x08)
+		IRQNoFlags () {5}
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0378, 0x0378, 0x04, 0x08)
+		IO (Decode16, 0x0778, 0x0778, 0x04, 0x08)
+		IRQNoFlags () {5}
+	})
+}
+
+Device (ENVC) {
+	Name (_HID, EISAID ("PNP0C02"))
+	Name (_UID, 1)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0230, 0x0230, 0x04, 0x10)
+		IO (Decode16, 0x0290, 0x0290, 0x04, 0x10)
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0230, 0x0230, 0x04, 0x10)
+		IO (Decode16, 0x0290, 0x0290, 0x04, 0x10)
+	})
+}
+
+Device (GPIC) {
+	Name (_HID, EISAID ("PNP0C02"))
+	Name (_UID, 2)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0300, 0x0300, 0x04, 0x20)
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x0300, 0x0300, 0x04, 0x20)
+	})
+}
diff --git a/src/mainboard/asus/am1i-a/acpi_tables.c b/src/mainboard/asus/am1i-a/acpi_tables.c
new file mode 100644
index 0000000000..47793139a0
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/acpi_tables.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write Yangtze IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+					   IO_APIC_ADDR, 0);
+
+	/* TODO: Remove the hardcode */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
+					   0xFEC20000, 24);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edge-triggered, Active high */
+
+	/* create all subtables for processors */
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
diff --git a/src/mainboard/asus/am1i-a/board_info.txt b/src/mainboard/asus/am1i-a/board_info.txt
new file mode 100644
index 0000000000..4873e82d5d
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/board_info.txt
@@ -0,0 +1,5 @@
+Category: mini
+Board URL: https://www.asus.com/us/Motherboards/AM1IA/
+ROM package: DIP8
+ROM protocol: SPI
+ROM socketed: y
diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c
new file mode 100644
index 0000000000..5e9b0d6f6e
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/buildOpts.c
@@ -0,0 +1,342 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ */
+
+#include <stdlib.h>
+#include "AGESA.h"
+
+#define INSTALL_FT3_SOCKET_SUPPORT           TRUE
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT   TRUE
+
+#define INSTALL_G34_SOCKET_SUPPORT  FALSE
+#define INSTALL_C32_SOCKET_SUPPORT  FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
+#define INSTALL_FP2_SOCKET_SUPPORT  FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
+#define INSTALL_FM2_SOCKET_SUPPORT  FALSE
+
+
+#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
+  #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
+    #undef INSTALL_FT3_SOCKET_SUPPORT
+    #define INSTALL_FT3_SOCKET_SUPPORT     FALSE
+  #endif
+#endif
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
+//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT          TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
+//#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT        TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
+#define BLDOPT_REMOVE_SRAT                     FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT                     FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA                     FALSE //TRUE
+#define	BLDOPT_REMOVE_CRAT			TRUE
+#define BLDOPT_REMOVE_CDIT                     TRUE
+#define BLDOPT_REMOVE_DMI                      TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
+
+//This element selects whether P-States should be forced to be independent,
+// as reported by the ACPI _PSD object. For single-link processors,
+// setting TRUE for OS to support this feature.
+
+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT  TRUE
+
+#define BLDCFG_PCI_MMIO_BASE	CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE	CONFIG_MMCONF_BUS_NUMBER
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT                  15000
+#define BLDCFG_VRM_NB_CURRENT_LIMIT               13000
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT          21000
+#define BLDCFG_VRM_SVI_OCP_LEVEL                  BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
+#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT       17000
+#define BLDCFG_VRM_NB_SVI_OCP_LEVEL               BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD            0
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         0
+#define BLDCFG_VRM_SLEW_RATE                      10000
+#define BLDCFG_VRM_NB_SLEW_RATE                   BLDCFG_VRM_SLEW_RATE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
+
+#define BLDCFG_PLAT_NUM_IO_APICS                 3
+#define BLDCFG_GNB_IOAPIC_ADDRESS		0xFEC20000
+#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE                   0
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0x1770 // Specifies the IO addresses trapped by the
+                                                         // core for C-state entry requests. A value
+                                                         // of 0 in this field specifies that the core
+                                                         // does not trap any IO addresses for C-state entry.
+                                                         // Values greater than 0xFFF8 results in undefined behavior.
+#define BLDCFG_PLATFORM_CSTATE_OPDATA             0x1770
+
+#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1600_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    FALSE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        FALSE
+#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
+#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE                       FALSE
+#define BLDCFG_BANK_SWIZZLE                       TRUE
+#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1333_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM                TRUE
+#define BLDCFG_USE_BURST_MODE                     FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE                 FALSE
+#define BLDCFG_ECC_REDIRECTION                    FALSE
+#define BLDCFG_SCRUB_DRAM_RATE                    0
+#define BLDCFG_SCRUB_L2_RATE                      0
+#define BLDCFG_SCRUB_L3_RATE                      0
+#define BLDCFG_SCRUB_IC_RATE                      0
+#define BLDCFG_SCRUB_DC_RATE                      0
+#define BLDCFG_ECC_SYNC_FLOOD                     FALSE
+#define BLDCFG_ECC_SYMBOL_SIZE                    4
+#define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000ul
+#define BLDCFG_1GB_ALIGN                          FALSE
+#define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE                UMA_AUTO
+#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeDisabled
+#define BLDCFG_IOMMU_SUPPORT                      FALSE
+#define OPTION_GFX_INIT_SVIEW                     FALSE
+//#define BLDCFG_PLATFORM_POWER_POLICY_MODE         BatteryLife
+
+//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL         OEM_LCD_BACK_LIGHT_CONTROL
+#define BLDCFG_CFG_ABM_SUPPORT                    TRUE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO                   TRUE
+//#define BLDCFG_IGPU_SUBSYSTEM_ID            OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID   OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID  OEM_APU_PCIE_PORTS_SSID
+
+#ifdef PCIEX_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
+#endif
+
+#define BLDCFG_PROCESSOR_SCOPE_NAME0              'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
+#define BLDCFG_PCIE_TRAINING_ALGORITHM           PcieTrainingDistributed
+
+/*  Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+/*
+ * Customized OEM build configurations for FCH component
+ */
+// #define BLDCFG_SMBUS0_BASE_ADDRESS            0xB00
+// #define BLDCFG_SMBUS1_BASE_ADDRESS            0xB20
+// #define BLDCFG_SIO_PME_BASE_ADDRESS           0xE00
+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0x400
+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0x404
+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS      0x408
+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0x410
+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS        0x420
+// #define BLDCFG_SPI_BASE_ADDRESS               0xFEC10000
+// #define BLDCFG_WATCHDOG_TIMER_BASE            0xFEC00000
+// #define BLDCFG_HPET_BASE_ADDRESS              0xFED00000
+// #define BLDCFG_SMI_CMD_PORT_ADDRESS           0xB0
+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS           0xFE00
+// #define BLDCFG_ROM_BASE_ADDRESS               0xFED61000
+// #define BLDCFG_AZALIA_SSID                    0x780D1022
+// #define BLDCFG_SMBUS_SSID                     0x780B1022
+// #define BLDCFG_IDE_SSID                       0x780C1022
+// #define BLDCFG_SATA_AHCI_SSID                 0x78011022
+// #define BLDCFG_SATA_IDE_SSID                  0x78001022
+// #define BLDCFG_SATA_RAID5_SSID                0x78031022
+// #define BLDCFG_SATA_RAID_SSID                 0x78021022
+// #define BLDCFG_EHCI_SSID                      0x78081022
+// #define BLDCFG_OHCI_SSID                      0x78071022
+// #define BLDCFG_LPC_SSID                       0x780E1022
+// #define BLDCFG_SD_SSID                        0x78061022
+// #define BLDCFG_XHCI_SSID                      0x78121022
+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB         FALSE
+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
+// #define BLDCFG_FCH_GPP_LINK_CONFIG            PortA4
+// #define BLDCFG_FCH_GPP_PORT0_PRESENT          FALSE
+// #define BLDCFG_FCH_GPP_PORT1_PRESENT          FALSE
+// #define BLDCFG_FCH_GPP_PORT2_PRESENT          FALSE
+// #define BLDCFG_FCH_GPP_PORT3_PRESENT          FALSE
+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG          FALSE
+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG          FALSE
+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG          FALSE
+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG          FALSE
+
+CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
+{
+  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+  { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+  { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+  { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+  { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+  { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+  { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+  { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+  { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+  { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList
+
+
+/*  Include the files that instantiate the configuration definitions.  */
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+                  // This is the delivery package title, "BrazosPI"
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+//#define DDR400_FREQUENCY   200     ///< DDR 400
+//#define DDR533_FREQUENCY   266     ///< DDR 533
+//#define DDR667_FREQUENCY   333     ///< DDR 667
+//#define DDR800_FREQUENCY   400     ///< DDR 800
+//#define DDR1066_FREQUENCY   533    ///< DDR 1066
+//#define DDR1333_FREQUENCY   667    ///< DDR 1333
+//#define DDR1600_FREQUENCY   800    ///< DDR 1600
+//#define DDR1866_FREQUENCY   933    ///< DDR 1866
+//#define DDR2100_FREQUENCY   1050   ///< DDR 2100
+//#define DDR2133_FREQUENCY   1066   ///< DDR 2133
+//#define DDR2400_FREQUENCY   1200   ///< DDR 2400
+//#define UNSUPPORTED_DDR_FREQUENCY		1201 ///< Highest limit of DDR frequency
+//
+///* QUANDRANK_TYPE*/
+//#define QUADRANK_REGISTERED				0 ///< Quadrank registered DIMM
+//#define QUADRANK_UNBUFFERED				1 ///< Quadrank unbuffered DIMM
+//
+///* USER_MEMORY_TIMING_MODE */
+//#define TIMING_MODE_AUTO				0 ///< Use best rate possible
+//#define TIMING_MODE_LIMITED				1 ///< Set user top limit
+//#define TIMING_MODE_SPECIFIC			2 ///< Set user specified speed
+//
+///* POWER_DOWN_MODE */
+//#define POWER_DOWN_BY_CHANNEL			0 ///< Channel power down mode
+//#define POWER_DOWN_BY_CHIP_SELECT		1 ///< Chip select power down mode
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define DFLT_SMBUS0_BASE_ADDRESS            0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS            0xB20
+#define DFLT_SIO_PME_BASE_ADDRESS           0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS     0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS     0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS      0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS     0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS        0x820
+#define DFLT_SPI_BASE_ADDRESS               0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS    0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS              0xFED00000
+#define DFLT_SMI_CMD_PORT                   0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS       0xFE00
+#define DFLT_GEC_BASE_ADDRESS               0xFED61000
+#define DFLT_AZALIA_SSID                    0x780D1022
+#define DFLT_SMBUS_SSID                     0x780B1022
+#define DFLT_IDE_SSID                       0x780C1022
+#define DFLT_SATA_AHCI_SSID                 0x78011022
+#define DFLT_SATA_IDE_SSID                  0x78001022
+#define DFLT_SATA_RAID5_SSID                0x78031022
+#define DFLT_SATA_RAID_SSID                 0x78021022
+#define DFLT_EHCI_SSID                      0x78081022
+#define DFLT_OHCI_SSID                      0x78071022
+#define DFLT_LPC_SSID                       0x780E1022
+#define DFLT_SD_SSID                        0x78061022
+#define DFLT_XHCI_SSID                      0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB         FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP     TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG            PortA4
+#define DFLT_FCH_GPP_PORT0_PRESENT          FALSE
+#define DFLT_FCH_GPP_PORT1_PRESENT          FALSE
+#define DFLT_FCH_GPP_PORT2_PRESENT          FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT          FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG          FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG          FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG          FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
+//#define BLDCFG_IR_PIN_CONTROL	0x33
+
+GPIO_CONTROL   imba180_gpio[] = {
+	{183, Function1, GpioIn | GpioOutEnB | PullUpB},
+	{-1}
+};
+//#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&imba180_gpio[0])
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0)
+#define DFLT_SCRUB_L2_RATE              (0)
+#define DFLT_SCRUB_L3_RATE              (0)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE              (5000)
+
+#include <PlatformInstall.h>
diff --git a/src/mainboard/asus/am1i-a/cmos.default b/src/mainboard/asus/am1i-a/cmos.default
new file mode 100644
index 0000000000..dcacda6795
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/cmos.default
@@ -0,0 +1,4 @@
+boot_option=Fallback
+debug_level=Spew
+sata_mode=IDE
+sata_speed=6Gbps
diff --git a/src/mainboard/asus/am1i-a/cmos.layout b/src/mainboard/asus/am1i-a/cmos.layout
new file mode 100644
index 0000000000..dfaa97d15b
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/cmos.layout
@@ -0,0 +1,63 @@
+#*****************************************************************************
+#
+#  This file is part of the coreboot project.
+#
+#  Copyright (C) 2012 Advanced Micro Devices, Inc.
+#  Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+#
+#  This program is free software; you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; version 2 of the License.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+#start-bit length  config config-ID    name
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+388          4       r       0        reboot_counter
+#392          3       r       0        unused
+#400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       r       0        boot_index
+432          8       r       0        boot_countdown
+440          8       e       10        sata_mode
+448          8       e       11        sata_speed
+#728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+enumerations
+
+#ID value   text
+#1     0     Disable
+#1     1     Enable
+4     0     Fallback
+4     1     Normal
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+10    0     IDE
+10    2     AHCI
+11    1     3Gbps
+11    0     6Gbps
+
+checksums
+
+checksum 392 455 984
diff --git a/src/mainboard/asus/am1i-a/devicetree.cb b/src/mainboard/asus/am1i-a/devicetree.cb
new file mode 100644
index 0000000000..b81048708a
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/devicetree.cb
@@ -0,0 +1,105 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2013 Advanced Micro Devices, Inc.
+# Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
+# Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family16kb/root_complex
+	device cpu_cluster 0 on
+		chip cpu/amd/agesa/family16kb
+			device lapic 0 on  end
+		end
+	end
+
+	device domain 0 on
+		subsystemid 0x1043 0x8623 inherit
+		chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
+			chip northbridge/amd/agesa/family16kb # PCI side of HT root complex
+				device pci 0.0 on  end  # Root Complex
+				device pci 1.0 on  end  # Internal Graphics P2P bridge 0x9804
+				device pci 1.1 on  end  # Internal Multimedia
+				device pci 2.0 on  end  # Host Bridge
+				device pci 2.1 on  end  # x4 PCIe slot
+				device pci 2.2 off  end # GPP Bridge 1 - not used
+				device pci 2.3 off  end # GPP Bridge 2 - not used
+				device pci 2.4 off  end # GPP Bridge 3 - not used
+				device pci 2.5 on  end  # Realtek GBE
+			end	#chip northbridge/amd/agesa/family16kb
+
+			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+				device pci 10.0 on  end # XHCI HC0
+				device pci 11.0 on  end # SATA
+				device pci 12.0 on  end # USB
+				device pci 12.2 on  end # USB
+				device pci 13.0 on  end # USB
+				device pci 13.2 on  end # USB
+				device pci 14.0 on      # SM
+					chip drivers/generic/generic #dimm 0-0-0
+						device i2c 50 on end
+					end
+					chip drivers/generic/generic #dimm 0-0-1
+						device i2c 51 on end
+					end
+				end # SM
+				device pci 14.2 on  end # HDA	0x4383
+				device pci 14.3 on      # LPC	0x439d
+					chip superio/ite/it8623e
+						device pnp 2e.0 off end		# FDC - not used
+						device pnp 2e.1 on		# COM1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.2 on		# COM2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 2e.3 on		# Parallel port
+							io 0x60 = 0x378
+							io 0x62 = 0x778		# for ECP mode
+							irq 0x70 = 5
+							drq 0x74 = 3
+						end
+						device pnp 2e.4 on		# EC
+							io 0x60 = 0x290
+							io 0x62 = 0x230
+						end
+						device pnp 2e.5 on		# PS/2 keyboard
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+						end
+						device pnp 2e.6 on		# PS/2 mouse
+							irq 0x70 = 12
+						end
+						device pnp 2e.7 on		# GPIO
+							io 0x62 = 0x300
+						end
+					end	#superio/ite/it8623e
+				end	#device pci 14.3 # LPC
+				device pci 14.7 off  end # SD - no card reader present
+			end	#chip southbridge/amd/agesa/hudson
+
+			device pci 18.0 on  end
+			device pci 18.1 on  end
+			device pci 18.2 on  end
+			device pci 18.3 on  end
+			device pci 18.4 on  end
+			device pci 18.5 on  end
+			register "spdAddrLookup" = "
+			{
+				{ {0xA0, 0xA2} },
+			}"
+
+		end	#chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
+	end	#domain
+end	#northbridge/amd/agesa/family16kb/root_complex
diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl
new file mode 100644
index 0000000000..4d91b2a16c
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/dsdt.asl
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
+ * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",	/* Output filename */
+	"DSDT",		/* Signature */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
+	"AMD   ",	/* OEMID */
+	"COREBOOT",	/* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include <arch/x86/acpi/debug.asl> */	/* Include global debug methods if needed */
+
+	/* Globals for the platform */
+	#include "acpi/mainboard.asl"
+
+	/* PCI IRQ mapping for the Southbridge */
+	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+	/* Describe the processor tree (\_PR) */
+	#include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
+
+	/* Contains the supported sleep states for this chipset */
+	#include <southbridge/amd/common/acpi/sleepstates.asl>
+
+	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
+	#include "acpi/sleep.asl"
+
+	/* System Bus */
+	Scope(\_SB) { /* Start \_SB scope */
+	 	/* global utility methods expected within the \_SB scope */
+		#include <arch/x86/acpi/globutil.asl>
+
+		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+		#include "acpi/routing.asl"
+
+		Device(PWRB) {
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})
+			Name(_STA, 0x0B)
+		}
+
+		Device(PCI0) {
+			/* Describe the AMD Northbridge */
+			#include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
+
+			/* Describe the AMD Fusion Controller Hub Southbridge */
+			#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+		}
+
+		/* Describe PCI INT[A-H] for the Southbridge */
+		#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+	} /* End \_SB scope */
+
+	/* Describe SMBUS for the Southbridge */
+	#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+	/* Define the System Indicators for the platform */
+	#include "acpi/si.asl"
+}
+/* End of ASL file */
diff --git a/src/mainboard/asus/am1i-a/irq_tables.c b/src/mainboard/asus/am1i-a/irq_tables.c
new file mode 100644
index 0000000000..c8ccbeb231
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/irq_tables.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,				/* u32 signature */
+	PIRQ_VERSION,				/* u16 version */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,	/* Max. number of devices on the bus */
+	0x00,					/* Interrupt router bus */
+	(0x14 << 3) | 0x3,			/* Interrupt router dev */
+	0,					/* IRQs devoted exclusively to PCI usage */
+	0x1002,					/* Vendor */
+	0x439d,					/* Device */
+	0,					/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	/* u8 rfu[11] */
+	0xa8,					/* Checksum (has to be set to some value that
+						* would give 0 after the sum of all bytes
+						* for this structure (including checksum).
+						*/
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x01 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x02 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0},
+		{0x00, (0x10 << 3) | 0x0, {{0x03, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x11 << 3) | 0x0, {{0x04, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x12 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x13 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x00, (0x14 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0},
+		{0x01, (0x00 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0},
+		{0x02, (0x00 << 3) | 0x0, {{0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/asus/am1i-a/mainboard.c b/src/mainboard/asus/am1i-a/mainboard.c
new file mode 100644
index 0000000000..9f00efde69
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/mainboard.c
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
+ * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <southbridge/amd/agesa/hudson/pci_devs.h>
+#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+#include <northbridge/amd/agesa/family16kb/pci_devs.h>
+
+const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
+	/* INTA# - INTH# */
+	[0x00] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,
+	/* Misc-nil,0,1,2, INT from Serial irq */
+	[0x08] = 0x5A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
+	[0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,
+	/* IMC INT0 - 5 */
+	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+	/* USB Devs 18/19 INTA-B */
+	[0x30] = 0x05,0x04,0x05,0x04,0x1F,0x1F,
+	/* RSVD, SATA */
+	[0x40] = 0x1F, 0x07
+};
+
+const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
+	/* INTA# - INTH# */
+	[0x00] = 0x10,0x11,0x12,0x13,0x1F,0x1F,0x1F,0x1F,
+	/* Misc-nil,0,1,2, INT from Serial irq */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
+	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x1F,
+	/* IMC INT0 - 5 */
+	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+	/* USB Devs 18/19 INTA-B */
+	[0x30] = 0x12,0x11,0x12,0x11,0x1F,0x1F,
+	/* RSVD, SATA */
+	[0x40] = 0x1F, 0x13
+};
+
+/*
+ * This table defines the index into the picr/intr_data
+ * tables for each device.  Any enabled device and slot
+ * that uses hardware interrupts should have an entry
+ * in this table to define its index into the FCH
+ * PCI_INTR register 0xC00/0xC01.  This index will define
+ * the interrupt that it should use.  Putting PIRQ_A into
+ * the PIN A index for a device will tell that device to
+ * use PIC IRQ 10 if it uses PIN A for its hardware INT.
+ */
+static const struct pirq_struct mainboard_pirq_data[] = {
+	/* {PCI_devfn,	{PIN A, PIN B, PIN C, PIN D}}, */
+	{GFX_DEVFN,	{PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}},			/* VGA:		01.0 */
+	{ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}},			/* Audio:	01.1 */
+	{NB_PCIE_PORT1_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},	/* x4 PCIe:	02.1 */
+	{NB_PCIE_PORT5_DEVFN,	{PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}},	/* Edge:	02.5 */
+	{XHCI_DEVFN,	{PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}},		/* XHCI:	10.0 */
+	{SATA_DEVFN,	{PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* SATA:	11.0 */
+	{OHCI1_DEVFN,	{PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI1:	12.0 */
+	{EHCI1_DEVFN,	{PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}},	/* EHCI1:	12.2 */
+	{OHCI2_DEVFN,	{PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI2:	13.0 */
+	{EHCI2_DEVFN,	{PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}},	/* EHCI2:	13.2 */
+	{HDA_DEVFN,		{PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},		/* HDA:		14.2 */
+};
+
+const u8 *picr_data = mainboard_picr_data;
+const u8 *intr_data = mainboard_intr_data;
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+	pirq_data_ptr = mainboard_pirq_data;
+	pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
+	intr_data_ptr = mainboard_intr_data;
+	picr_data_ptr = mainboard_picr_data;
+}
+
+/**********************************************
+ * enable the dedicated function in mainboard.
+ **********************************************/
+static void mainboard_enable(device_t dev)
+{
+	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+	/* Initialize the PIRQ data structures for consumption */
+	pirq_setup();
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c
new file mode 100644
index 0000000000..bc7853b14d
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/mptable.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+#include <drivers/generic/ioapic/chip.h>
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	int bus_isa;
+
+	/*
+	 * By the time this function gets called, the IOAPIC registers
+	 * have been written so they can be read to get the correct
+	 * APIC ID and Version
+	 */
+	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+	/* Intialize the MP_Table */
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LOCAL_APIC_ADDR);
+
+	/*
+	 * Type 0: Processor Entries:
+	 * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
+	 * CPU Signature (Stepping, Model, Family),
+	 * Feature Flags
+	 */
+	smp_write_processors(mc);
+
+	/*
+	 * Type 1: Bus Entries:
+	 * Bus ID, Bus Type
+	 */
+	mptable_write_buses(mc, NULL, &bus_isa);
+
+	/*
+	 * Type 2: I/O APICs:
+	 * APIC ID, Version, APIC Flags:EN, Address
+	 */
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+	/*
+	 * Type 3: I/O Interrupt Table Entries:
+	 * Int Type, Int Polarity, Int Level, Source Bus ID,
+	 * Source Bus IRQ, Dest APIC ID, Dest PIN#
+	 */
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#define PCI_INT(bus, dev, fn, pin) \
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
+
+	/* APU Internal Graphic Device */
+	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]);
+
+	/* GPP Ports */
+	PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]);
+	PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]);
+	PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]);
+	PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]);
+
+	/* SATA */
+	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
+
+	/* USB */
+	PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); /* XHCI */
+	PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
+	PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
+
+	/* Southbridge HD Audio */
+	PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_HDA]);
+
+	/* PCIe slot & Onboard NIC */
+	PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]);
+	PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]);
+	PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]);
+	PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]);
+	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_B]);
+
+	/*Local Ints:	 Type	Polarity	Trigger	 Bus ID	 IRQ	APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+		smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c
new file mode 100644
index 0000000000..d62052f08f
--- /dev/null
+++ b/src/mainboard/asus/am1i-a/romstage.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
+ * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#include <commonlib/loglevel.h>
+#include <northbridge/amd/agesa/state_machine.h>
+#include <southbridge/amd/common/amd_defs.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8623e/it8623e.h>
+
+#define ITE_CONFIG_REG_CC	0x02
+#define SERIAL_DEV		PNP_DEV(0x2e, IT8623E_SP2)
+#define GPIO_DEV		PNP_DEV(0x2e, IT8623E_GPIO)
+#define CLKIN_DEV		PNP_DEV(0x2e, IT8623E_GPIO)
+#define ENVC_DEV		PNP_DEV(0x2e, IT8623E_EC)
+
+/* Sets up EC configuration as per vendor defaults */
+static void ite_evc_conf(pnp_devfn_t dev)
+{
+	pnp_set_enable(dev, 0);
+	ite_reg_write(dev, 0x70, 0x00);
+	ite_reg_write(dev, 0xf0, 0x00);
+	ite_reg_write(dev, 0xf1, 0x00);
+	ite_reg_write(dev, 0xf2, 0x06);
+	ite_reg_write(dev, 0xf3, 0x00);
+	ite_reg_write(dev, 0xf4, 0x00);
+	ite_reg_write(dev, 0xf5, 0x36);
+	ite_reg_write(dev, 0xf6, 0x03);
+	ite_reg_write(dev, 0xf9, 0x48);
+	ite_reg_write(dev, 0xfa, 0x00);
+	ite_reg_write(dev, 0xfb, 0x10);
+	pnp_set_enable(dev, 1);
+}
+
+/*
+ * Sets up GPIO configuration as per vendor defaults
+ * SIO defaults are unknown therefore all GPIO pins are configured
+*/
+static void ite_gpio_conf(pnp_devfn_t dev)
+{
+	ite_reg_write(dev, 0x23, 0x08);
+	ite_reg_write(dev, 0x25, 0x10);
+	ite_reg_write(dev, 0x26, 0x00);
+	ite_reg_write(dev, 0x27, 0x80);
+	ite_reg_write(dev, 0x28, 0x45);
+	ite_reg_write(dev, 0x29, 0x00);
+	ite_reg_write(dev, 0x2a, 0x00);
+	ite_reg_write(dev, 0x2b, 0x48);
+	ite_reg_write(dev, 0x2c, 0x10);
+	ite_reg_write(dev, 0x2d, 0x80);
+	ite_reg_write(dev, 0x71, 0x00);
+	ite_reg_write(dev, 0x72, 0x00);
+	ite_reg_write(dev, 0x73, 0x38);
+	ite_reg_write(dev, 0x74, 0x00);
+	ite_reg_write(dev, 0xb0, 0x00);
+	ite_reg_write(dev, 0xb1, 0x00);
+	ite_reg_write(dev, 0xb2, 0x00);
+	ite_reg_write(dev, 0xb3, 0x00);
+	ite_reg_write(dev, 0xb4, 0x00);
+	ite_reg_write(dev, 0xb8, 0x00);
+	ite_reg_write(dev, 0xb9, 0x00);
+	ite_reg_write(dev, 0xba, 0x00);
+	ite_reg_write(dev, 0xbb, 0x00);
+	ite_reg_write(dev, 0xbc, 0x00);
+	ite_reg_write(dev, 0xbd, 0x00);
+	ite_reg_write(dev, 0xc0, 0x01);
+	ite_reg_write(dev, 0xc1, 0x00);
+	ite_reg_write(dev, 0xc2, 0x00);
+	ite_reg_write(dev, 0xc3, 0x00);
+	ite_reg_write(dev, 0xc4, 0x00);
+	ite_reg_write(dev, 0xc8, 0x01);
+	ite_reg_write(dev, 0xc9, 0x00);
+	ite_reg_write(dev, 0xca, 0x00);
+	ite_reg_write(dev, 0xcb, 0x00);
+	ite_reg_write(dev, 0xcc, 0x00);
+	ite_reg_write(dev, 0xcd, 0x20);
+	ite_reg_write(dev, 0xce, 0x00);
+	ite_reg_write(dev, 0xcf, 0x00);
+	ite_reg_write(dev, 0xe0, 0x00);
+	ite_reg_write(dev, 0xe1, 0x00);
+	ite_reg_write(dev, 0xe2, 0x00);
+	ite_reg_write(dev, 0xe3, 0x00);
+	ite_reg_write(dev, 0xe4, 0x00);
+	ite_reg_write(dev, 0xe9, 0x21);
+	ite_reg_write(dev, 0xf0, 0x00);
+	ite_reg_write(dev, 0xf1, 0x00);
+	ite_reg_write(dev, 0xf2, 0x00);
+	ite_reg_write(dev, 0xf3, 0x00);
+	ite_reg_write(dev, 0xf4, 0x00);
+	ite_reg_write(dev, 0xf5, 0x00);
+	ite_reg_write(dev, 0xf6, 0x00);
+	ite_reg_write(dev, 0xf7, 0x00);
+	ite_reg_write(dev, 0xf8, 0x00);
+	ite_reg_write(dev, 0xf9, 0x00);
+	ite_reg_write(dev, 0xfa, 0x00);
+	ite_reg_write(dev, 0xfb, 0x00);
+}
+
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+	int i;
+	u32 t32, val;
+	u8 byte;
+	pci_devfn_t dev;
+	u32 *addr32;
+
+	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+	 * LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
+	 * even though the register is not documented in the Kabini BKDG.
+	 * Otherwise the serial output is bad code.
+	 */
+	outb(0xD2, 0xcd6);
+	outb(0x00, 0xcd7);
+
+	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
+	outb(0xEA, 0xcd6);
+	outb(0x1, 0xcd7);
+
+	/* Set LPC decode enables. */
+	pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
+	pci_write_config32(dev2, 0x44, 0xff03ffd5);
+
+	hudson_lpc_port80();
+
+	/* Enable the AcpiMmio space */
+	outb(0x24, 0xcd6);
+	outb(0x1, 0xcd7);
+
+	/* Configure ClkDrvStr1 settings */
+	addr32 = (u32 *)0xfed80e24;
+	t32 = *addr32;
+	t32 = 0x030800aa;
+	*addr32 = t32;
+
+	/* Configure MiscClkCntl1 settings */
+	addr32 = (u32 *)0xfed80e40;
+	t32 = *addr32;
+	t32 = 0x000c4050;
+	*addr32 = t32;
+
+	/* enable SIO LPC decode */
+	dev = PCI_DEV(0, 0x14, 3);
+	byte = pci_read_config8(dev, 0x48);
+	byte |= 3;	/* 2e, 2f & 4e, 4f */
+	pci_write_config8(dev, 0x48, byte);
+
+	ite_gpio_conf(GPIO_DEV);
+	ite_evc_conf(ENVC_DEV);
+
+	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	ite_kill_watchdog(GPIO_DEV);
+
+	/*
+	* On Larne, after LpcClkDrvSth is set, it needs some time to be stable,
+	* because of the buffer ICS551M
+	*/
+	for (i = 0; i < 200000; i++)
+		val = inb(0xcd6);
+}