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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-12 00:10:38 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-23 20:34:11 +0000 |
| commit | 41114650d0aa508f5629f32b1d78683eae2974ce (patch) | |
| tree | 98646bb27ada639043385fb8234da432ba2865cc /src | |
| parent | e5dcaf12693daf56fde73fbf9af5ee1bd5e10883 (diff) | |
| download | coreboot-41114650d0aa508f5629f32b1d78683eae2974ce.tar.xz | |
sb/intel/i82801jx: Add function to detect s3 resume
File copied from i82801gx.
Change-Id: I107087b6448f18b6a5ae21c2ae0392c057dd23b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/i82801jx/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/early_lpc.c | 54 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/i82801jx.h | 1 |
3 files changed, 56 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 9121c3d964..d6a3a7ddf5 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -37,5 +37,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c +romstage-y += early_lpc.c endif diff --git a/src/southbridge/intel/i82801jx/early_lpc.c b/src/southbridge/intel/i82801jx/early_lpc.c new file mode 100644 index 0000000000..74f0ee2920 --- /dev/null +++ b/src/southbridge/intel/i82801jx/early_lpc.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <timestamp.h> +#include <cpu/x86/tsc.h> +#include <console/console.h> +#include <arch/acpi.h> +#include "i82801jx.h" + +uint64_t get_initial_timestamp(void) +{ + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; + return tsc_to_uint64(base_time); +} + +int southbridge_detect_s3_resume(void) +{ + u32 reg32; + + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { + if (!acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + return 1; + } + } + + return 0; +} diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 1c765a3d9c..9dddd2e922 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -226,6 +226,7 @@ int smbus_read_byte(unsigned device, unsigned address); void i82801jx_early_init(void); void i82801jx_dmi_setup(void); void i82801jx_dmi_poll_vc1(void); +int southbridge_detect_s3_resume(void); #endif #endif |