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authorMats Erik Andersson <mats.andersson@gisladisker.se>2008-09-30 04:52:29 +0000
committerPeter Stuge <peter@stuge.se>2008-09-30 04:52:29 +0000
commit45db366d5c8222148100713b165762aab61c478f (patch)
tree4c84616895aca41cdabef8a1fce066c9204d41d0 /src
parent166ad2d7a56b6b472bb573eb331370733482610c (diff)
downloadcoreboot-45db366d5c8222148100713b165762aab61c478f.tar.xz
A duplicate register address is incremented in table register_values.
A trivial fix to correct the address of the high byte in SDRAMC. Thus the leadoff timing IPDLT will be correctly referenced. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/i440bx/raminit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index c480f0a5b9..38470eab20 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -282,7 +282,7 @@ static const long register_values[] = {
* 1 = 2 clocks of RAS# precharge
*/
SDRAMC + 0, 0x00, 0x00,
- SDRAMC + 0, 0x00, 0x00,
+ SDRAMC + 1, 0x00, 0x00,
/* PGPOL - Paging Policy Register
* 0x78 - 0x79