diff options
| author | Naresh G Solanki <naresh.solanki@intel.com> | 2018-04-05 11:22:12 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-09 09:28:41 +0000 |
| commit | 4764be33e04aacc6f22645249046ed0524aaa529 (patch) | |
| tree | 97a05328fed779f9ad26d11c7c784741985aac1c /src | |
| parent | 7632ce03920ae3dfdced2e7d856bf988c0aa3835 (diff) | |
| download | coreboot-4764be33e04aacc6f22645249046ed0524aaa529.tar.xz | |
soc/intel/{apl,glk}: Move flush_l1d_to_l2 function to common location
Move flush_l1d_l2 function to common location within the SoC.
BUG=None:
BRANCH=None
TEST= Build for glkrvp.
Change-Id: I4aaaaccc4f343bc4926111258a33e09e79c76141
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/25547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/car.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/cpu.h | 10 |
2 files changed, 11 insertions, 7 deletions
diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index f46e0f89ec..920580d0a1 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -20,19 +20,13 @@ #include <cpu/x86/msr.h> #include <intelblocks/msr.h> #include <program_loading.h> +#include <soc/cpu.h> /* * This file supports the necessary hoops one needs to jump through since * early FSP component and early stages are running from cache-as-ram. */ -static void flush_l1d_to_l2(void) -{ - msr_t msr = rdmsr(MSR_POWER_MISC); - msr.lo |= FLUSH_DL1_L2; - wrmsr(MSR_POWER_MISC, msr); -} - static inline int is_car_addr(uintptr_t addr) { return ((addr >= CONFIG_DCACHE_RAM_BASE) && diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index ed4a7de477..4a1a7a438c 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -18,6 +18,9 @@ #ifndef _SOC_APOLLOLAKE_CPU_H_ #define _SOC_APOLLOLAKE_CPU_H_ +#include <cpu/x86/msr.h> +#include <intelblocks/msr.h> + /* Common Timer Copy (CTC) frequency - 19.2MHz. */ #define CTC_FREQ 19200000 @@ -25,4 +28,11 @@ struct device; void apollolake_init_cpus(struct device *dev); void mainboard_devtree_update(struct device *dev); +/* Flush L1D to L2 */ +static inline void flush_l1d_to_l2(void) +{ + msr_t msr = rdmsr(MSR_POWER_MISC); + msr.lo |= FLUSH_DL1_L2; + wrmsr(MSR_POWER_MISC, msr); +} #endif /* _SOC_APOLLOLAKE_CPU_H_ */ |