armv7: Clean out weak symbols and unnecessary #ifdef's in cache files

This just removes unused code. If for some reason we don't want to
initialize cache, then the CPU or mainboard specific init routines
don't need to call these.

Change-Id: Ieb7393b6cbc103e490753da4ed27114156466ded
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2209
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

2 files changed, 0 insertions, 140 deletions

diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c
index 1786725148..c684d65dfd 100644
--- a/src/arch/armv7/lib/cache-cp15.c
+++ b/src/arch/armv7/lib/cache-cp15.c
@@ -21,25 +21,13 @@
  * MA 02111-1307 USA
  */
 
-/* FIXME(dhendrix): clean-up weak symbols if it looks unlikely we'll
-   want to override them with anything other than what's in cache_v7. */
 #include <common.h>
 #include <stdlib.h>
 #include <system.h>
 #include <global_data.h>
 
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-
 DECLARE_GLOBAL_DATA_PTR;
 
-#if 0
-void __arm_init_before_mmu(void)
-{
-}
-void arm_init_before_mmu(void)
-	__attribute__((weak, alias("__arm_init_before_mmu")));
-#endif
-
 static void cp_delay (void)
 {
 	volatile int i;
@@ -92,11 +80,6 @@ void __mmu_page_table_flush(unsigned long start, unsigned long stop)
 }
 #endif
 
-#if 0
-void mmu_page_table_flush(unsigned long start, unsigned long stop)
-	__attribute__((weak, alias("__mmu_page_table_flush")));
-#endif
-
 void mmu_set_region_dcache(unsigned long start, int size, enum dcache_option option)
 {
 	u32 *page_table = (u32 *)gd->tlb_addr;
@@ -237,24 +220,7 @@ static void cache_disable(uint32_t cache_bit)
 		flush_dcache_all();
 	set_cr(reg & ~cache_bit);
 }
-#endif
-
-#ifdef CONFIG_SYS_ICACHE_OFF
-void icache_enable (void)
-{
-	return;
-}
-
-void icache_disable (void)
-{
-	return;
-}
 
-int icache_status (void)
-{
-	return 0;					/* always off */
-}
-#else
 void icache_enable(void)
 {
 	cache_enable(CR_I);
@@ -269,24 +235,7 @@ int icache_status(void)
 {
 	return (get_cr() & CR_I) != 0;
 }
-#endif
-
-#ifdef CONFIG_SYS_DCACHE_OFF
-void dcache_enable (void)
-{
-	return;
-}
 
-void dcache_disable (void)
-{
-	return;
-}
-
-int dcache_status (void)
-{
-	return 0;					/* always off */
-}
-#else
 void dcache_enable(void)
 {
 	cache_enable(CR_C);
@@ -301,4 +250,3 @@ int dcache_status(void)
 {
 	return (get_cr() & CR_C) != 0;
 }
-#endif
diff --git a/src/arch/armv7/lib/cache_v7.c b/src/arch/armv7/lib/cache_v7.c
index 13bb59f025..22c3f898af 100644
--- a/src/arch/armv7/lib/cache_v7.c
+++ b/src/arch/armv7/lib/cache_v7.c
@@ -32,7 +32,6 @@
 #define ARMV7_DCACHE_INVAL_RANGE	3
 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
 
-#ifndef CONFIG_SYS_DCACHE_OFF
 /*
  * Write the level and type you want to Cache Size Selection Register(CSSELR)
  * to get size details from Current Cache Size ID Register(CCSIDR)
@@ -319,43 +318,7 @@ void  flush_cache(unsigned long start, unsigned long size)
 {
 	flush_dcache_range(start, start + size);
 }
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
-ulong dcache_get_line_size(void)
-{
-	return 0;
-}
-
-void invalidate_dcache_all(void)
-{
-}
-
-void flush_dcache_all(void)
-{
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
 
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void arm_init_before_mmu(void)
-{
-}
-
-void  flush_cache(unsigned long start, unsigned long size)
-{
-}
-
-void mmu_page_table_flush(unsigned long start, unsigned long stop)
-{
-}
-
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
-
-#ifndef CONFIG_SYS_ICACHE_OFF
 /* Invalidate entire I-cache and branch predictor array */
 void invalidate_icache_all(void)
 {
@@ -374,54 +337,3 @@ void invalidate_icache_all(void)
 	/* ISB - make sure the instruction stream sees it */
 	CP15ISB;
 }
-#else
-void invalidate_icache_all(void)
-{
-}
-#endif
-
-/*
- * FIXME(dhendrix): had unexplainable compilation failure of weak symbols
- * (in spite of having prototypes and whatnot)... ron's advice is "death
- *  to weak symbols!"
- */
-#if 0
-/*
- * Stub implementations for outer cache operations
- */
-void __v7_outer_cache_enable(void)
-{
-}
-void v7_outer_cache_enable(void)
-	__attribute__((weak, alias("__v7_outer_cache_enable")));
-
-void __v7_outer_cache_disable(void)
-{
-}
-void v7_outer_cache_disable(void)
-	__attribute__((weak, alias("__v7_outer_cache_disable")));
-
-void __v7_outer_cache_flush_all(void)
-{
-}
-void v7_outer_cache_flush_all(void)
-	__attribute__((weak, alias("__v7_outer_cache_flush_all")));
-
-void __v7_outer_cache_inval_all(void)
-{
-}
-void v7_outer_cache_inval_all(void)
-	__attribute__((weak, alias("__v7_outer_cache_inval_all")));
-
-void __v7_outer_cache_flush_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_flush_range(u32 start, u32 end)
-	__attribute__((weak, alias("__v7_outer_cache_flush_range")));
-
-void __v7_outer_cache_inval_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_inval_range(u32 start, u32 end)
-	__attribute__((weak, alias("__v7_outer_cache_inval_range")));
-#endif