diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-12-16 17:11:27 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-02-04 17:43:49 +0100 |
| commit | 50c3ba24d4969aa33454325abe1a4a25ef4bcc94 (patch) | |
| tree | 1c1c73af435c25266cd09eada2c25fb99d29336a /src | |
| parent | 4121f9e555170bde6589b4e731f17f2149c3b401 (diff) | |
| download | coreboot-50c3ba24d4969aa33454325abe1a4a25ef4bcc94.tar.xz | |
intel/skylake: unconditionally set SPI controller BAR
The setting of the SPI controller BAR was conditional
on the nominal frequency being set. Therefore, that doesn't
mean the SPI BAR is set on all boots. Move the setting of
the BAR in the southbridge_bootblock_init() which is called
prioer to cpu_bootblock_init().
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Confirmed spibar is always set on glados.
Change-Id: Ia58447d70f5e39a4336d4d08593f143332de833a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 56fff7c25c2eb0ccd90e08f71c064b83c66640f8
Original-Change-Id: I1e0cff783f4b072b80589a3a84703a262b86be3a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/319461
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13587
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/bootblock/cpu.c | 18 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/pch.c | 22 |
2 files changed, 23 insertions, 17 deletions
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 6fc4d92662..d713974358 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -74,25 +74,9 @@ static void bootblock_mdelay(int ms) static void set_pch_cpu_strap(u8 flex_ratio) { - device_t dev = PCH_DEV_SPI; uint8_t *spibar = (void *)SPI_BASE_ADDRESS; u32 ssl, ssms, soft_reset_data; - u8 pcireg; - - /* Assign Resources to SPI Controller */ - /* Clear BIT 1-2 SPI Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for SPI */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, - SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY); - - /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); + /* Set Strap Lock Disable */ ssl = read32(spibar + SPIBAR_RESET_LOCK); diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 1bde80254e..94ed844d3b 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -30,7 +30,29 @@ static void enable_spi_prefetch(void) pci_write_config8(PCH_DEV_SPI, 0xdc, reg8); } +static void enable_spibar(void) +{ + device_t dev = PCH_DEV_SPI; + u8 pcireg; + + /* Assign Resources to SPI Controller */ + /* Clear BIT 1-2 SPI Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for SPI */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, + SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + static void bootblock_southbridge_init(void) { + enable_spibar(); enable_spi_prefetch(); } |