build system: rename __BOOT_BLOCK__ and __VER_STAGE__

Drop the inner underscore for consistency. Follows the
commit stated below.

Change-Id: I75cde6e2cd55d2c0fbb5a2d125c359d91e14cf6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-on-Change-Id: I6a1f25f7077328a8b5201a79b18fc4c2e22d0b06
Based-on-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-on-Reviewed-on: https://chromium-review.googlesource.com/219172
Reviewed-on: http://review.coreboot.org/9290
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)

9 files changed, 16 insertions, 16 deletions

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index e7903aa464..e4af06d875 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -98,9 +98,9 @@ endif
 bootblock_inc += $(objgenerated)/bootblock.inc
 bootblock_inc += $(src)/arch/x86/lib/walkcbfs.S
 
-bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__
+bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 ifeq ($(CONFIG_SSE),y)
-bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__
+bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
 endif
 
 $(objgenerated)/bootblock.ld: $(obj)/ldoptions $$(filter %.ld,$$(bootblock-srcs))
diff --git a/src/console/init.c b/src/console/init.c
index e638216d1c..ee64d87cb2 100644
--- a/src/console/init.c
+++ b/src/console/init.c
@@ -49,7 +49,7 @@ void console_init(void)
 
 	printk(BIOS_INFO, "\n\ncoreboot-%s%s %s %s starting...\n",
 		      coreboot_version, coreboot_extra_version, coreboot_build,
-#if defined(__BOOT_BLOCK__)
+#if defined(__BOOTBLOCK__)
 		      "bootblock"
 #elif defined(__PRE_RAM__)
 		      "romstage"
diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c
index f189aeae02..a8e21514d3 100644
--- a/src/cpu/allwinner/a10/clock.c
+++ b/src/cpu/allwinner/a10/clock.c
@@ -130,7 +130,7 @@ void a1x_gate_dram_clock_output(void)
  * Linker doesn't garbage collect and the function below adds about half
  * kilobyte to the bootblock, and log2_ceil is not available in the bootblock.
  */
-#ifndef __BOOT_BLOCK__
+#ifndef __BOOTBLOCK__
 
 #define PLL1_CFG(N, K, M, P_EXP)	\
 	((1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | 16 << 20 | 2 << 13) | \
@@ -270,4 +270,4 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
 	udelay(1);
 }
 
-#endif  /* __BOOT_BLOCK__ */
+#endif  /* __BOOTBLOCK__ */
diff --git a/src/include/rules.h b/src/include/rules.h
index 5740b77a4a..a99d3e20d0 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -23,7 +23,7 @@
  * romstage, ramstage or SMM.
  */
 
-#if defined(__BOOT_BLOCK__)
+#if defined(__BOOTBLOCK__)
 #define ENV_BOOTBLOCK 1
 #define ENV_ROMSTAGE 0
 #define ENV_RAMSTAGE 0
diff --git a/src/lib/cbfs_core.h b/src/lib/cbfs_core.h
index c1eecd25a3..221fe5d34d 100644
--- a/src/lib/cbfs_core.h
+++ b/src/lib/cbfs_core.h
@@ -13,7 +13,7 @@
 # define CBFS_MINI_BUILD
 #elif defined(__SMM__)
 # define CBFS_MINI_BUILD
-#elif defined(__BOOT_BLOCK__)
+#elif defined(__BOOTBLOCK__)
   /* No LZMA in boot block. */
 #elif defined(__PRE_RAM__) && !CONFIG_COMPRESS_RAMSTAGE
   /* No LZMA in romstage if ramstage is not compressed. */
diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
index e06c8d6bee..bdbb4a56dc 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h
@@ -300,7 +300,7 @@
 #define GPSSUS_GPIO_F1_RANGE_START	11
 #define GPSSUS_GPIO_F1_RANGE_END	21
 
-#ifndef __BOOT_BLOCK__
+#ifndef __BOOTBLOCK__
 
 struct soc_gpio_map {
 	u32 pad_conf0;
@@ -344,7 +344,7 @@ uint8_t read_ssus_gpio(uint8_t gpio_num);
 void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
 void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
 
-#endif /* #ifndef __BOOT_BLOCK__ */
+#endif /* #ifndef __BOOTBLOCK__ */
 
 /* Functions / defines for changing GPIOs in romstage */
 /* SCORE Pad definitions. */
@@ -385,7 +385,7 @@ static inline void ssus_select_func(int pad, int func)
 	write32(pconf0_addr, reg);
 }
 
-#ifndef __BOOT_BLOCK__
+#ifndef __BOOTBLOCK__
 
 /* These functions require that the input pad be configured as an input GPIO */
 static inline int score_get_gpio(int pad)
@@ -408,6 +408,6 @@ static inline void ssus_disable_internal_pull(int pad)
 	write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
 }
 
-#endif /* #ifndef __BOOT_BLOCK__ */
+#endif /* #ifndef __BOOTBLOCK__ */
 
 #endif /* _BAYTRAIL_GPIO_H_ */
diff --git a/src/soc/samsung/exynos5250/gpio.c b/src/soc/samsung/exynos5250/gpio.c
index 2a93328a70..3e50791ede 100644
--- a/src/soc/samsung/exynos5250/gpio.c
+++ b/src/soc/samsung/exynos5250/gpio.c
@@ -211,7 +211,7 @@ int gpio_set_value(unsigned gpio, int value)
  */
 #define GPIO_DELAY_US 5
 
-#ifndef __BOOT_BLOCK__
+#ifndef __BOOTBLOCK__
 /*
  * FIXME(dhendrix): These functions use udelay, which has dependencies on
  * pwm code and timer code. These aren't necessary for the bootblock and
@@ -252,7 +252,7 @@ int gpio_read_mvl3(unsigned gpio)
 
 	return value;
 }
-#endif	/* __BOOT_BLOCK__ */
+#endif	/* __BOOTBLOCK__ */
 
 /*
  * Display Exynos GPIO information
diff --git a/src/soc/samsung/exynos5420/gpio.c b/src/soc/samsung/exynos5420/gpio.c
index 2b65eda04e..ac82bf7eb1 100644
--- a/src/soc/samsung/exynos5420/gpio.c
+++ b/src/soc/samsung/exynos5420/gpio.c
@@ -211,7 +211,7 @@ int gpio_set_value(unsigned gpio, int value)
  */
 #define GPIO_DELAY_US	15
 
-#ifndef __BOOT_BLOCK__
+#ifndef __BOOTBLOCK__
 /*
  * FIXME(dhendrix): These functions use udelay, which has dependencies on
  * pwm code and timer code. These aren't necessary for the bootblock and
@@ -252,7 +252,7 @@ int gpio_read_mvl3(unsigned gpio)
 
 	return value;
 }
-#endif	/* __BOOT_BLOCK__ */
+#endif	/* __BOOTBLOCK__ */
 
 /*
  * Display Exynos GPIO information
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index 91287b5cfa..c445135587 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -96,7 +96,7 @@ VB_SOURCE := vboot_reference
 CPPFLAGS_common += -I$(VB_SOURCE)/firmware/2lib/include
 CPPFLAGS_common += -I$(VB_SOURCE)/firmware/include
 
-verstage-generic-ccopts += -D__PRE_RAM__ -D__VER_STAGE__
+verstage-generic-ccopts += -D__PRE_RAM__ -D__VERSTAGE__
 
 ifeq ($(CONFIG_RETURN_FROM_VERSTAGE),y)
 bootblock-y += verstub.c chromeos.c