diff options
author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-04-10 04:15:23 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2011-04-10 04:15:23 +0000 |
commit | 61aee5f4b1d596a0cb007e666df13094abed6d10 (patch) | |
tree | bd37c86c07a3d98d24b1ea47defe2fbe2b877ad4 /src | |
parent | df6fd566ba6f8541ee5611e57bfbab58b632a269 (diff) | |
download | coreboot-61aee5f4b1d596a0cb007e666df13094abed6d10.tar.xz |
In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html
It's about time we follow this advice.
Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and
drop unused CPP define
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/x86/Makefile.bigbootblock.inc | 2 | ||||
-rw-r--r-- | src/arch/x86/Makefile.bootblock.inc | 4 | ||||
-rw-r--r-- | src/arch/x86/Makefile.inc | 2 | ||||
-rw-r--r-- | src/include/cpu/amd/gx2def.h | 2 | ||||
-rw-r--r-- | src/include/cpu/amd/lxdef.h | 2 | ||||
-rw-r--r-- | src/include/cpu/amd/mtrr.h | 2 | ||||
-rw-r--r-- | src/include/cpu/x86/mtrr.h | 4 | ||||
-rw-r--r-- | src/include/fallback.h | 4 | ||||
-rw-r--r-- | src/mainboard/amd/serengeti_cheetah/ap_romstage.c | 3 | ||||
-rw-r--r-- | src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c | 3 | ||||
-rw-r--r-- | src/mainboard/gigabyte/m57sli/ap_romstage.c | 3 | ||||
-rw-r--r-- | src/mainboard/msi/ms7260/ap_romstage.c | 4 | ||||
-rw-r--r-- | src/mainboard/nvidia/l1_2pvv/ap_romstage.c | 3 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dme/ap_romstage.c | 3 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dmr/ap_romstage.c | 3 | ||||
-rw-r--r-- | src/mainboard/tyan/s2912/ap_romstage.c | 3 | ||||
-rw-r--r-- | src/southbridge/amd/cs5535/cs5535.h | 2 | ||||
-rw-r--r-- | src/southbridge/amd/cs5536/cs5536.h | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 2 |
20 files changed, 15 insertions, 40 deletions
diff --git a/src/arch/x86/Makefile.bigbootblock.inc b/src/arch/x86/Makefile.bigbootblock.inc index a6b8e11bca..d486a03f9b 100644 --- a/src/arch/x86/Makefile.bigbootblock.inc +++ b/src/arch/x86/Makefile.bigbootblock.inc @@ -26,7 +26,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDI $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/crt0.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< -o $@ $(obj)/coreboot: $$(romstage-objs) $(obj)/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/Makefile.bootblock.inc b/src/arch/x86/Makefile.bootblock.inc index 4958a77cb7..f076238a7e 100644 --- a/src/arch/x86/Makefile.bootblock.inc +++ b/src/arch/x86/Makefile.bootblock.inc @@ -55,7 +55,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o: $(obj)/mainboard/$(MAINBOARDDIR)/b $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" @@ -105,5 +105,5 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDI $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 98498e0c8f..a2fb71d4c6 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -225,7 +225,7 @@ else $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -I$(src) -I. -I$(obj) -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@ + $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h index 97b7eef1f0..c0467beccb 100644 --- a/src/include/cpu/amd/gx2def.h +++ b/src/include/cpu/amd/gx2def.h @@ -511,7 +511,7 @@ #define PMLogic_BASE (0x9D00) -#if !defined(__ROMCC__) && !defined(ASSEMBLY) +#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(void); void SystemPreInit(void); diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index 16a22ba10f..6d0a78c847 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -630,7 +630,7 @@ #define DELAY_UPPER_DISABLE_CLK135 (1 << 23) #define DELAY_LOWER_STATUS_MASK 0x7C0 -#if !defined(__ROMCC__) && !defined(ASSEMBLY) +#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated); void SystemPreInit(void); diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 6e25aa3e5e..c0d6b51c36 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -33,7 +33,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -#if !defined(__PRE_RAM__) && !defined(ASSEMBLY) +#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) void amd_setup_mtrrs(void); #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index f9aadc58a5..6ab6bec015 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -36,7 +36,7 @@ #define MTRRfix4K_F0000_MSR 0x26e #define MTRRfix4K_F8000_MSR 0x26f -#if !defined (ASSEMBLY) && !defined(__PRE_RAM__) +#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) #include <device/device.h> void enable_fixed_mtrr(void); void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); @@ -69,7 +69,7 @@ void x86_setup_fixed_mtrrs(void); #endif -#if !defined (ASSEMBLY) +#if !defined (__ASSEMBLER__) #if defined(CONFIG_XIP_ROM_SIZE) # if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK extern unsigned long AUTO_XIP_ROM_BASE; diff --git a/src/include/fallback.h b/src/include/fallback.h index b639452bac..ffcbafb6e1 100644 --- a/src/include/fallback.h +++ b/src/include/fallback.h @@ -1,12 +1,12 @@ #ifndef FALLBACK_H #define FALLBACK_H -#if !defined(ASSEMBLY) && !defined(__PRE_RAM__) +#if !defined(__ASSEMBLER__) && !defined(__PRE_RAM__) void set_boot_successful(void); void boot_successful(void); -#endif /* ASSEMBLY */ +#endif /* __ASSEMBLER__ */ #define RTC_BOOT_BYTE 48 diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index ca59458ce8..126b464305 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c index 51902b4bbb..b1574542d7 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c @@ -21,9 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c index c9c0de1c66..2b4be30d25 100644 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c index 418bb09084..7a93e8b343 100644 --- a/src/mainboard/msi/ms7260/ap_romstage.c +++ b/src/mainboard/msi/ms7260/ap_romstage.c @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c index 438ed58cf5..c1c49cca90 100644 --- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index 6904b6d51b..ebd0305bf9 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index e56561e746..62d796aa1c 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c index 8b7805b03a..6310759ced 100644 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ b/src/mainboard/tyan/s2912/ap_romstage.c @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> diff --git a/src/southbridge/amd/cs5535/cs5535.h b/src/southbridge/amd/cs5535/cs5535.h index 590811c604..0db7c17551 100644 --- a/src/southbridge/amd/cs5535/cs5535.h +++ b/src/southbridge/amd/cs5535/cs5535.h @@ -115,7 +115,7 @@ /* Flash Memory Mask values */ #define FLASH_MEM_4K 0xFFFFF000 -#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if defined(__PRE_RAM__) void cs5535_disable_internal_uart(void); #else diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index a80c0680c5..8fa24daf38 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -442,7 +442,7 @@ #define FLASH_IO_128B 0x0000FF80 #define FLASH_IO_256B 0x0000FF00 -#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if defined(__PRE_RAM__) void cs5536_setup_onchipuart(int uart); void cs5536_disable_internal_uart(void); diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 709b8327a8..3b461b5365 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#if !defined(ASSEMBLY) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #if !defined(__ACPI__) /* dsdt include */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 208ff6d4af..63c583dea5 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -38,7 +38,7 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); 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