soc/intel/cannonlake: Fix CNL-H GPIO pin map

The GPIO pin map for CNL-H does not match with the OS expected
pin numbers.  This has been updated to match what is used by the
Linux kernel pinctrl driver and the pad base has been set for
the GPIO groups to match the sparse GPIO map used by the kernel.

I do not have CNL-H hardware to test this so it is verified against
the kernel driver at drivers/pinctrl/intel/pinctrl-cannonlake.c

Change-Id: Ife7d3090d654b0b88c6911befa08bf6abd4f2ff9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30134
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 340 insertions, 224 deletions

diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c
index 939a38e6a8..f0fc79dccb 100644
--- a/src/soc/intel/cannonlake/gpio_cnp_h.c
+++ b/src/soc/intel/cannonlake/gpio_cnp_h.c
@@ -32,38 +32,58 @@ static const struct reset_mapping rst_map_com0[] = {
 	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
 };
 
+/*
+ * The GPIO driver for Cannonlake on Windows/Linux expects 32 GPIOs per pad
+ * group, regardless of whether or not there is a physical pad for each
+ * exposed GPIO number.
+ *
+ * This results in the OS having a sparse GPIO map, and devices that need
+ * to export an ACPI GPIO must use the OS expected number.
+ *
+ * Not all pins are usable as GPIO and those groups do not have a pad base.
+ *
+ * This layout matches the Linux kernel pinctrl map for CNL-H at:
+ * linux/drivers/pinctrl/intel/pinctrl-cannonlake.c
+ */
 static const struct pad_group cnl_community0_groups[] = {
-	INTEL_GPP(GPP_A0, GPP_A0, GPP_A23),		/* GPP_A */
-	INTEL_GPP(GPP_A0, GPP_B0, GPP_B23),		/* GPP_B */
+	INTEL_GPP_BASE(GPP_A0, GPP_A0, GPIO_RSVD_0, 0),		/* GPP_A */
+	INTEL_GPP_BASE(GPP_A0, GPP_B0, GPIO_RSVD_2, 32),	/* GPP_B */
 };
 
 static const struct pad_group cnl_community1_groups[] = {
-	INTEL_GPP(GPP_C0, GPP_C0, GPP_C23),		/* GPP_C */
-	INTEL_GPP(GPP_C0, GPP_D0, GPP_D23),		/* GPP_D */
-	INTEL_GPP(GPP_C0, GPP_G0, GPP_G7),		/* GPP_G */
+	INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 64),		/* GPP_C */
+	INTEL_GPP_BASE(GPP_C0, GPP_D0, GPP_D23, 96),		/* GPP_D */
+	INTEL_GPP_BASE(GPP_C0, GPP_G0, GPP_G7, 128),		/* GPP_G */
+	INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_10),		/* AZA */
+	INTEL_GPP_BASE(GPP_C0, GPIO_RSVD_11, GPIO_RSVD_42, 160),/* VGPIO_0 */
+	INTEL_GPP(GPP_C0, GPIO_RSVD_43, GPIO_RSVD_50),		/* VGPIO_0 */
 };
 
+/* This community is not visible to the OS */
 static const struct pad_group cnl_community2_groups[] = {
-	INTEL_GPP(GPD0, GPD0, GPD11),			/* GPD */
+	INTEL_GPP(GPD0, GPD0, GPD11),				/* GPD */
 };
 
 static const struct pad_group cnl_community3_groups[] = {
-	INTEL_GPP(GPP_K0, GPP_K0, GPP_K23),		/* GPP_K*/
-	INTEL_GPP(GPP_K0, GPP_H0, GPP_H23),		/* GPP_H */
-	INTEL_GPP(GPP_K0, GPP_E0, GPP_E12),		/* GPP_E */
-	INTEL_GPP(GPP_K0, GPP_F0, GPP_F23),		/* GPP_F */
+	INTEL_GPP_BASE(GPP_K0, GPP_K0, GPP_K23, 192),		/* GPP_K */
+	INTEL_GPP_BASE(GPP_K0, GPP_H0, GPP_H23, 224),		/* GPP_H */
+	INTEL_GPP_BASE(GPP_K0, GPP_E0, GPP_E12, 256),		/* GPP_E */
+	INTEL_GPP_BASE(GPP_K0, GPP_F0, GPP_F23, 288),		/* GPP_F */
+	INTEL_GPP(GPP_K0, GPIO_RSVD_51, GPIO_RSVD_59),		/* SPI */
 };
 
 static const struct pad_group cnl_community4_groups[] = {
-	INTEL_GPP(GPP_I0, GPP_I0, GPP_I14),		/* GPP_I */
-	INTEL_GPP(GPP_I0, GPP_J0, GPP_J11),		/* GPP_J */
+	INTEL_GPP(GPIO_RSVD_60, GPIO_RSVD_60, GPIO_RSVD_70),	/* CPU */
+	INTEL_GPP(GPIO_RSVD_60, GPIO_RSVD_71, GPIO_RSVD_79),	/* JTAG */
+	INTEL_GPP_BASE(GPIO_RSVD_60, GPP_I0, GPP_I14, 320),	/* GPP_I */
+	INTEL_GPP_BASE(GPIO_RSVD_60, GPP_J0, GPP_J11, 352),	/* GPP_J */
 };
 
 static const struct pad_community cnl_communities[] = {
 	{ /* GPP A, B */
 		.port = PID_GPIOCOM0,
 		.first_pad = GPP_A0,
-		.last_pad = GPP_B23,
+		.last_pad = GPIO_RSVD_2,
 		.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -79,7 +99,7 @@ static const struct pad_community cnl_communities[] = {
 	}, { /* GPP C, D, G */
 		.port = PID_GPIOCOM1,
 		.first_pad = GPP_C0,
-		.last_pad = GPP_G7,
+		.last_pad = GPIO_RSVD_50,
 		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -111,7 +131,7 @@ static const struct pad_community cnl_communities[] = {
 	}, { /* GPP K, H, E, F */
 		.port = PID_GPIOCOM3,
 		.first_pad = GPP_K0,
-		.last_pad = GPP_F23,
+		.last_pad = GPIO_RSVD_59,
 		.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -126,7 +146,7 @@ static const struct pad_community cnl_communities[] = {
 		.num_groups = ARRAY_SIZE(cnl_community3_groups),
 	}, { /* GPP I, J */
 		.port = PID_GPIOCOM4,
-		.first_pad = GPP_I0,
+		.first_pad = GPIO_RSVD_60,
 		.last_pad = GPP_J11,
 		.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
index 203632d5bb..95f7e419cf 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
@@ -66,242 +66,338 @@
 #define GPP_A21			21
 #define GPP_A22			22
 #define GPP_A23			23
+#define GPIO_RSVD_0		24
 
 /* Group B */
-#define GPP_B0			24
-#define GPP_B1			25
-#define GPP_B2			26
-#define GPP_B3			27
-#define GPP_B4			28
-#define GPP_B5			29
-#define GPP_B6			30
-#define GPP_B7			31
-#define GPP_B8			32
-#define GPP_B9			33
-#define GPP_B10			34
-#define GPP_B11			35
-#define GPP_B12			36
-#define GPP_B13			37
-#define GPP_B14			38
-#define GPP_B15			39
-#define GPP_B16			40
-#define GPP_B17			41
-#define GPP_B18			42
-#define GPP_B19			43
-#define GPP_B20			44
-#define GPP_B21			45
-#define GPP_B22			46
-#define GPP_B23			47
+#define GPP_B0			25
+#define GPP_B1			26
+#define GPP_B2			27
+#define GPP_B3			28
+#define GPP_B4			29
+#define GPP_B5			30
+#define GPP_B6			31
+#define GPP_B7			32
+#define GPP_B8			33
+#define GPP_B9			34
+#define GPP_B10			35
+#define GPP_B11			36
+#define GPP_B12			37
+#define GPP_B13			38
+#define GPP_B14			39
+#define GPP_B15			40
+#define GPP_B16			41
+#define GPP_B17			42
+#define GPP_B18			43
+#define GPP_B19			44
+#define GPP_B20			45
+#define GPP_B21			46
+#define GPP_B22			47
+#define GPP_B23			48
+#define GPIO_RSVD_1		49
+#define GPIO_RSVD_2		50
 
-#define NUM_GPIO_COM0_PADS	(GPP_B23 - GPP_A0 + 1)
+#define NUM_GPIO_COM0_PADS	(GPIO_RSVD_2 - GPP_A0 + 1)
 
 /* Group C */
-#define GPP_C0			48
-#define GPP_C1			49
-#define GPP_C2			50
-#define GPP_C3			51
-#define GPP_C4			52
-#define GPP_C5			53
-#define GPP_C6			54
-#define GPP_C7			55
-#define GPP_C8			56
-#define GPP_C9			57
-#define GPP_C10			58
-#define GPP_C11			59
-#define GPP_C12			60
-#define GPP_C13			61
-#define GPP_C14			62
-#define GPP_C15			63
-#define GPP_C16			64
-#define GPP_C17			65
-#define GPP_C18			66
-#define GPP_C19			67
-#define GPP_C20			68
-#define GPP_C21			69
-#define GPP_C22			70
-#define GPP_C23			71
+#define GPP_C0			51
+#define GPP_C1			52
+#define GPP_C2			53
+#define GPP_C3			54
+#define GPP_C4			55
+#define GPP_C5			56
+#define GPP_C6			57
+#define GPP_C7			58
+#define GPP_C8			59
+#define GPP_C9			60
+#define GPP_C10			61
+#define GPP_C11			62
+#define GPP_C12			63
+#define GPP_C13			64
+#define GPP_C14			65
+#define GPP_C15			66
+#define GPP_C16			67
+#define GPP_C17			68
+#define GPP_C18			69
+#define GPP_C19			70
+#define GPP_C20			71
+#define GPP_C21			72
+#define GPP_C22			73
+#define GPP_C23			74
 
 /* Group D */
-#define GPP_D0			72
-#define GPP_D1			73
-#define GPP_D2			74
-#define GPP_D3			75
-#define GPP_D4			76
-#define GPP_D5			77
-#define GPP_D6			78
-#define GPP_D7			79
-#define GPP_D8			80
-#define GPP_D9			81
-#define GPP_D10			82
-#define GPP_D11			83
-#define GPP_D12			84
-#define GPP_D13			85
-#define GPP_D14			86
-#define GPP_D15			87
-#define GPP_D16			88
-#define GPP_D17			89
-#define GPP_D18			90
-#define GPP_D19			91
-#define GPP_D20			92
-#define GPP_D21			93
-#define GPP_D22			94
-#define GPP_D23			95
+#define GPP_D0			75
+#define GPP_D1			76
+#define GPP_D2			77
+#define GPP_D3			78
+#define GPP_D4			79
+#define GPP_D5			80
+#define GPP_D6			81
+#define GPP_D7			82
+#define GPP_D8			83
+#define GPP_D9			84
+#define GPP_D10			85
+#define GPP_D11			86
+#define GPP_D12			87
+#define GPP_D13			88
+#define GPP_D14			89
+#define GPP_D15			90
+#define GPP_D16			91
+#define GPP_D17			92
+#define GPP_D18			93
+#define GPP_D19			94
+#define GPP_D20			95
+#define GPP_D21			96
+#define GPP_D22			97
+#define GPP_D23			98
 
 /* Group G */
-#define GPP_G0			96
-#define GPP_G1			97
-#define GPP_G2			98
-#define GPP_G3			99
-#define GPP_G4			100
-#define GPP_G5			101
-#define GPP_G6			102
-#define GPP_G7			103
+#define GPP_G0			99
+#define GPP_G1			100
+#define GPP_G2			101
+#define GPP_G3			102
+#define GPP_G4			103
+#define GPP_G5			104
+#define GPP_G6			105
+#define GPP_G7			106
 
-#define NUM_GPIO_COM1_PADS	(GPP_G7 - GPP_C0 + 1)
+/* AZA */
+#define GPIO_RSVD_3		107
+#define GPIO_RSVD_4		108
+#define GPIO_RSVD_5		109
+#define GPIO_RSVD_6		110
+#define GPIO_RSVD_7		111
+#define GPIO_RSVD_8		112
+#define GPIO_RSVD_9		113
+#define GPIO_RSVD_10		114
+
+/* VGPIO_0 */
+#define GPIO_RSVD_11		115
+#define GPIO_RSVD_12		116
+#define GPIO_RSVD_13		117
+#define GPIO_RSVD_14		118
+#define GPIO_RSVD_15		119
+#define GPIO_RSVD_16		120
+#define GPIO_RSVD_17		121
+#define GPIO_RSVD_18		122
+#define GPIO_RSVD_19		123
+#define GPIO_RSVD_20		124
+#define GPIO_RSVD_21		125
+#define GPIO_RSVD_22		126
+#define GPIO_RSVD_23		127
+#define GPIO_RSVD_24		128
+#define GPIO_RSVD_25		129
+#define GPIO_RSVD_26		130
+#define GPIO_RSVD_27		131
+#define GPIO_RSVD_28		132
+#define GPIO_RSVD_29		133
+#define GPIO_RSVD_30		134
+#define GPIO_RSVD_31		135
+#define GPIO_RSVD_32		136
+#define GPIO_RSVD_33		137
+#define GPIO_RSVD_34		138
+#define GPIO_RSVD_35		139
+#define GPIO_RSVD_36		140
+#define GPIO_RSVD_37		141
+#define GPIO_RSVD_38		142
+#define GPIO_RSVD_39		143
+#define GPIO_RSVD_40		144
+#define GPIO_RSVD_41		145
+#define GPIO_RSVD_42		146
+
+/* VGPIO_1 */
+#define GPIO_RSVD_43		147
+#define GPIO_RSVD_44		148
+#define GPIO_RSVD_45		149
+#define GPIO_RSVD_46		150
+#define GPIO_RSVD_47		151
+#define GPIO_RSVD_48		152
+#define GPIO_RSVD_49		153
+#define GPIO_RSVD_50		154
+
+#define NUM_GPIO_COM1_PADS	(GPIO_RSVD_50 - GPP_C0 + 1)
 
 /* Group K */
-#define GPP_K0			104
-#define GPP_K1			105
-#define GPP_K2			106
-#define GPP_K3			107
-#define GPP_K4			108
-#define GPP_K5			109
-#define GPP_K6			110
-#define GPP_K7			111
-#define GPP_K8			112
-#define GPP_K9			113
-#define GPP_K10			114
-#define GPP_K11			115
-#define GPP_K12			116
-#define GPP_K13			117
-#define GPP_K14			118
-#define GPP_K15			119
-#define GPP_K16			120
-#define GPP_K17			121
-#define GPP_K18			122
-#define GPP_K19			123
-#define GPP_K20			124
-#define GPP_K21			125
-#define GPP_K22			126
-#define GPP_K23			127
+#define GPP_K0			155
+#define GPP_K1			156
+#define GPP_K2			157
+#define GPP_K3			158
+#define GPP_K4			159
+#define GPP_K5			160
+#define GPP_K6			161
+#define GPP_K7			162
+#define GPP_K8			163
+#define GPP_K9			164
+#define GPP_K10			165
+#define GPP_K11			166
+#define GPP_K12			167
+#define GPP_K13			168
+#define GPP_K14			169
+#define GPP_K15			170
+#define GPP_K16			171
+#define GPP_K17			172
+#define GPP_K18			173
+#define GPP_K19			174
+#define GPP_K20			175
+#define GPP_K21			176
+#define GPP_K22			177
+#define GPP_K23			178
 
 /* Group H */
-#define GPP_H0			128
-#define GPP_H1			129
-#define GPP_H2			130
-#define GPP_H3			131
-#define GPP_H4			132
-#define GPP_H5			133
-#define GPP_H6			134
-#define GPP_H7			135
-#define GPP_H8			136
-#define GPP_H9			137
-#define GPP_H10			138
-#define GPP_H11			139
-#define GPP_H12			140
-#define GPP_H13			141
-#define GPP_H14			142
-#define GPP_H15			143
-#define GPP_H16			144
-#define GPP_H17			145
-#define GPP_H18			146
-#define GPP_H19			147
-#define GPP_H20			148
-#define GPP_H21			149
-#define GPP_H22			150
-#define GPP_H23			151
+#define GPP_H0			179
+#define GPP_H1			180
+#define GPP_H2			181
+#define GPP_H3			182
+#define GPP_H4			183
+#define GPP_H5			184
+#define GPP_H6			185
+#define GPP_H7			186
+#define GPP_H8			187
+#define GPP_H9			188
+#define GPP_H10			189
+#define GPP_H11			190
+#define GPP_H12			191
+#define GPP_H13			192
+#define GPP_H14			193
+#define GPP_H15			194
+#define GPP_H16			195
+#define GPP_H17			196
+#define GPP_H18			197
+#define GPP_H19			198
+#define GPP_H20			199
+#define GPP_H21			200
+#define GPP_H22			201
+#define GPP_H23			202
 
 /* Group E */
-#define GPP_E0			152
-#define GPP_E1			153
-#define GPP_E2			154
-#define GPP_E3			155
-#define GPP_E4			156
-#define GPP_E5			157
-#define GPP_E6			158
-#define GPP_E7			159
-#define GPP_E8			160
-#define GPP_E9			161
-#define GPP_E10			162
-#define GPP_E11			163
-#define GPP_E12			164
+#define GPP_E0			203
+#define GPP_E1			204
+#define GPP_E2			205
+#define GPP_E3			206
+#define GPP_E4			207
+#define GPP_E5			208
+#define GPP_E6			209
+#define GPP_E7			210
+#define GPP_E8			211
+#define GPP_E9			212
+#define GPP_E10			213
+#define GPP_E11			214
+#define GPP_E12			215
 
 /* Group F */
-#define GPP_F0			165
-#define GPP_F1			166
-#define GPP_F2			167
-#define GPP_F3			168
-#define GPP_F4			169
-#define GPP_F5			170
-#define GPP_F6			171
-#define GPP_F7			172
-#define GPP_F8			173
-#define GPP_F9			174
-#define GPP_F10			175
-#define GPP_F11			176
-#define GPP_F12			177
-#define GPP_F13			178
-#define GPP_F14			179
-#define GPP_F15			180
-#define GPP_F16			181
-#define GPP_F17			182
-#define GPP_F18			183
-#define GPP_F19			184
-#define GPP_F20			185
-#define GPP_F21			186
-#define GPP_F22			187
-#define GPP_F23			188
+#define GPP_F0			216
+#define GPP_F1			217
+#define GPP_F2			218
+#define GPP_F3			219
+#define GPP_F4			220
+#define GPP_F5			221
+#define GPP_F6			222
+#define GPP_F7			223
+#define GPP_F8			224
+#define GPP_F9			225
+#define GPP_F10			226
+#define GPP_F11			227
+#define GPP_F12			228
+#define GPP_F13			229
+#define GPP_F14			230
+#define GPP_F15			231
+#define GPP_F16			232
+#define GPP_F17			233
+#define GPP_F18			234
+#define GPP_F19			235
+#define GPP_F20			236
+#define GPP_F21			237
+#define GPP_F22			238
+#define GPP_F23			239
+
+/* SPI */
+#define GPIO_RSVD_51		240
+#define GPIO_RSVD_52		241
+#define GPIO_RSVD_53		242
+#define GPIO_RSVD_54		243
+#define GPIO_RSVD_55		244
+#define GPIO_RSVD_56		245
+#define GPIO_RSVD_57		246
+#define GPIO_RSVD_58		247
+#define GPIO_RSVD_59		248
 
-#define NUM_GPIO_COM3_PADS	(GPP_F23 - GPP_K0 + 1)
+#define NUM_GPIO_COM3_PADS	(GPIO_RSVD_59 - GPP_K0 + 1)
+
+/* CPU */
+#define GPIO_RSVD_60		249
+#define GPIO_RSVD_61		250
+#define GPIO_RSVD_62		251
+#define GPIO_RSVD_63		252
+#define GPIO_RSVD_64		253
+#define GPIO_RSVD_65		254
+#define GPIO_RSVD_66		255
+#define GPIO_RSVD_67		256
+#define GPIO_RSVD_68		257
+#define GPIO_RSVD_69		258
+#define GPIO_RSVD_70		259
+
+/* JTAG */
+#define GPIO_RSVD_71		260
+#define GPIO_RSVD_72		261
+#define GPIO_RSVD_73		262
+#define GPIO_RSVD_74		263
+#define GPIO_RSVD_75		264
+#define GPIO_RSVD_76		265
+#define GPIO_RSVD_77		266
+#define GPIO_RSVD_78		267
+#define GPIO_RSVD_79		268
 
 /* Group I */
-#define GPP_I0			189
-#define GPP_I1			190
-#define GPP_I2			191
-#define GPP_I3			192
-#define GPP_I4			193
-#define GPP_I5			194
-#define GPP_I6			195
-#define GPP_I7			196
-#define GPP_I8			197
-#define GPP_I9			198
-#define GPP_I10			199
-#define GPP_I11			200
-#define GPP_I12			201
-#define GPP_I13			202
-#define GPP_I14			203
+#define GPP_I0			269
+#define GPP_I1			270
+#define GPP_I2			271
+#define GPP_I3			272
+#define GPP_I4			273
+#define GPP_I5			274
+#define GPP_I6			275
+#define GPP_I7			276
+#define GPP_I8			277
+#define GPP_I9			278
+#define GPP_I10			279
+#define GPP_I11			280
+#define GPP_I12			281
+#define GPP_I13			282
+#define GPP_I14			283
+#define GPIO_RSVD_80		284
+#define GPIO_RSVD_81		285
+#define GPIO_RSVD_82		286
 
 /* Group J */
-#define GPP_J0			204
-#define GPP_J1			205
-#define GPP_J2			206
-#define GPP_J3			207
-#define GPP_J4			208
-#define GPP_J5			209
-#define GPP_J6			210
-#define GPP_J7			211
-#define GPP_J8			212
-#define GPP_J9			213
-#define GPP_J10			214
-#define GPP_J11			215
+#define GPP_J0			287
+#define GPP_J1			288
+#define GPP_J2			289
+#define GPP_J3			290
+#define GPP_J4			291
+#define GPP_J5			292
+#define GPP_J6			293
+#define GPP_J7			294
+#define GPP_J8			295
+#define GPP_J9			296
+#define GPP_J10			297
+#define GPP_J11			298
 
 #define NUM_GPIO_COM4_PADS	(GPP_J11 - GPP_I0 + 1)
 
 /* Group GPD  */
-#define GPD0			216
-#define GPD1			217
-#define GPD2			218
-#define GPD3			219
-#define GPD4			220
-#define GPD5			221
-#define GPD6			222
-#define GPD7			223
-#define GPD8			224
-#define GPD9			225
-#define GPD10			226
-#define GPD11			227
+#define GPD0			299
+#define GPD1			300
+#define GPD2			301
+#define GPD3			302
+#define GPD4			303
+#define GPD5			304
+#define GPD6			305
+#define GPD7			306
+#define GPD8			307
+#define GPD9			308
+#define GPD10			309
+#define GPD11			310
 
 #define NUM_GPIO_COM2_PADS	(GPD11 - GPD0 + 1)
 
-#define TOTAL_PADS			(GPD11 + 1)
+#define TOTAL_PADS		(GPD11 + 1)
+
 #endif