diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-03-12 01:22:01 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-23 09:35:51 +0000 |
| commit | 6975e07997cedf8a78f0704a461765dfe2a09fe6 (patch) | |
| tree | 138b7bee3e2482d7a95ad4dfb9bf0d401f7b97f0 /src | |
| parent | 79a219813b3e8186f5e89b2e0cd9f8a921fa088f (diff) | |
| download | coreboot-6975e07997cedf8a78f0704a461765dfe2a09fe6.tar.xz | |
mb/tglrvp: Update Audio AIC settings for Tiger Lake
Update Audio AIC UPD settings and gpio pad configs for Tiger Lake.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I45935b79f6fa4ad66238eead9258a4f15feec508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src')
4 files changed, 34 insertions, 23 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 41a361c016..23737c3070 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -101,7 +101,9 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "0" + register "PchHdaAudioLinkSspEnable[2]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T register "PchHdaIDispLinkTmode" = "2" # iDisp-Link Freq 4: 96MHz, 3: 48MHz. diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 4b600e6d0b..758a21c5c9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -60,10 +60,12 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C5, 1, DEEP), PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2S_MCLK2 */ + /* CNVi */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ - }; /* Early pad configuration in bootblock */ @@ -71,23 +73,24 @@ static const struct pad_config early_gpio_table[] = { /* Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ - PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), /* I2S0_HP_TX */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_HP_RX */ + PAD_CFG_NF(GPP_R4, DN_20K, DEEP, NF1), /* HDA_RST_L */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SPKR_SCLK */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_SPKR_TX */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_SPKR_RX */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S2_SPKR_SCLK */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* I2S2_SPKR_SFRM */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* I2S2_SPKR_TX */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* I2S2_SPKR_RX */ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SNDW0_HP_CLK */ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW0_HP_DATA */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), /* SNDW1_SPKR_CLK */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* SNDW1_SPKR_DATA */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC0_CLK_B */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK_A */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC1_CLK_B */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK_A */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ /* DP */ PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* L_BKLTEN */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 586fd26da7..f2e5510147 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -97,7 +97,9 @@ chip soc/intel/tigerlake register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSspEnable[0]" = "1" - register "PchHdaAudioLinkSspEnable[1]" = "1" + register "PchHdaAudioLinkSspEnable[1]" = "0" + register "PchHdaAudioLinkSspEnable[2]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T register "PchHdaIDispLinkTmode" = "2" # iDisp-Link Freq 4: 96MHz, 3: 48MHz. diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 3ee9ec7022..219786535a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -60,6 +60,9 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C5, 1, DEEP), PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2S_MCLK2 */ + }; /* Early pad configuration in bootblock */ @@ -67,23 +70,24 @@ static const struct pad_config early_gpio_table[] = { /* Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ - PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), /* I2S0_HP_TX */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_HP_RX */ + PAD_CFG_NF(GPP_R4, DN_20K, DEEP, NF1), /* HDA_RST_L */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SPKR_SCLK */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_SPKR_TX */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_SPKR_RX */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S2_SPKR_SCLK */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* I2S2_SPKR_SFRM */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* I2S2_SPKR_TX */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* I2S2_SPKR_RX */ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SNDW0_HP_CLK */ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW0_HP_DATA */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), /* SNDW1_SPKR_CLK */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* SNDW1_SPKR_DATA */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC0_CLK_B */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK_A */ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC1_CLK_B */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK_A */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */ /* DP */ PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* L_BKLTEN */ |