bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurable

DRAM reset gate GPIO is different on different mobos move it to hidden config
with 60 (current value) as default.

Set it to 10 for Lenovo X201.

Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4622
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

5 files changed, 82 insertions, 38 deletions

diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig
index a2d66b3724..76be9db0ac 100644
--- a/src/mainboard/lenovo/x201/Kconfig
+++ b/src/mainboard/lenovo/x201/Kconfig
@@ -43,6 +43,10 @@ config IRQ_SLOT_COUNT
 	int
 	default 18
 
+config DRAM_RESET_GATE_GPIO
+	int
+	default 10
+
 config MAX_CPUS
 	int
 	default 4
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index c2720ef4c7..d060dae406 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -45,6 +45,10 @@ config EHCI_DEBUG_OFFSET
 	hex
 	default 0xa0
 
+config DRAM_RESET_GATE_GPIO
+	int
+	default 60
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/intel/bd82x6x/bootblock.c"
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 99f6b51319..f886ad4432 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -290,6 +290,31 @@ static void busmaster_disable_on_bus(int bus)
         }
 }
 
+static void southbridge_gate_memory_reset_real(int offset,
+					       u16 use, u16 io, u16 lvl)
+{
+	u32 reg32;
+
+	/* Make sure it is set as GPIO */
+	reg32 = inl(use);
+	if (!(reg32 & (1 << offset))) {
+		reg32 |= (1 << offset);
+		outl(reg32, use);
+	}
+
+	/* Make sure it is set as output */
+	reg32 = inl(io);
+	if (reg32 & (1 << offset)) {
+		reg32 &= ~(1 << offset);
+		outl(reg32, io);
+	}
+
+	/* Drive the output low */
+	reg32 = inl(lvl);
+	reg32 &= ~(1 << offset);
+	outl(reg32, lvl);
+}
+
 /*
  * Drive GPIO 60 low to gate memory reset in S3.
  *
@@ -298,31 +323,22 @@ static void busmaster_disable_on_bus(int bus)
  */
 static void southbridge_gate_memory_reset(void)
 {
-	u32 reg32;
 	u16 gpiobase;
 
 	gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
 	if (!gpiobase)
 		return;
 
-	/* Make sure it is set as GPIO */
-	reg32 = inl(gpiobase + GPIO_USE_SEL2);
-	if (!(reg32 & (1 << 28))) {
-		reg32 |= (1 << 28);
-		outl(reg32, gpiobase + GPIO_USE_SEL2);
-	}
-
-	/* Make sure it is set as output */
-	reg32 = inl(gpiobase + GP_IO_SEL2);
-	if (reg32 & (1 << 28)) {
-		reg32 &= ~(1 << 28);
-		outl(reg32, gpiobase + GP_IO_SEL2);
-	}
-
-	/* Drive the output low */
-	reg32 = inl(gpiobase + GP_LVL2);
-	reg32 &= ~(1 << 28);
-	outl(reg32, gpiobase + GP_LVL2);
+	if (CONFIG_DRAM_RESET_GATE_GPIO >= 32)
+		southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32,
+						   gpiobase + GPIO_USE_SEL2,
+						   gpiobase + GP_IO_SEL2,
+						   gpiobase + GP_LVL2);
+	else
+		southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO,
+						   gpiobase + GPIO_USE_SEL,
+						   gpiobase + GP_IO_SEL,
+						   gpiobase + GP_LVL);
 }
 
 static void xhci_sleep(u8 slp_typ)
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index 07e714b77e..97d5883222 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -43,6 +43,10 @@ config EHCI_DEBUG_OFFSET
 	hex
 	default 0xa0
 
+config DRAM_RESET_GATE_GPIO
+	int
+	default 60
+
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/intel/bd82x6x/bootblock.c"
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index 5ee8ef9538..bc4ca22c59 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -290,6 +290,31 @@ static void busmaster_disable_on_bus(int bus)
         }
 }
 
+static void southbridge_gate_memory_reset_real(int offset,
+					       u16 use, u16 io, u16 lvl)
+{
+	u32 reg32;
+
+	/* Make sure it is set as GPIO */
+	reg32 = inl(use);
+	if (!(reg32 & (1 << offset))) {
+		reg32 |= (1 << offset);
+		outl(reg32, use);
+	}
+
+	/* Make sure it is set as output */
+	reg32 = inl(io);
+	if (reg32 & (1 << offset)) {
+		reg32 &= ~(1 << offset);
+		outl(reg32, io);
+	}
+
+	/* Drive the output low */
+	reg32 = inl(lvl);
+	reg32 &= ~(1 << offset);
+	outl(reg32, lvl);
+}
+
 /*
  * Drive GPIO 60 low to gate memory reset in S3.
  *
@@ -298,31 +323,22 @@ static void busmaster_disable_on_bus(int bus)
  */
 static void southbridge_gate_memory_reset(void)
 {
-	u32 reg32;
 	u16 gpiobase;
 
 	gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
 	if (!gpiobase)
 		return;
 
-	/* Make sure it is set as GPIO */
-	reg32 = inl(gpiobase + GPIO_USE_SEL2);
-	if (!(reg32 & (1 << 28))) {
-		reg32 |= (1 << 28);
-		outl(reg32, gpiobase + GPIO_USE_SEL2);
-	}
-
-	/* Make sure it is set as output */
-	reg32 = inl(gpiobase + GP_IO_SEL2);
-	if (reg32 & (1 << 28)) {
-		reg32 &= ~(1 << 28);
-		outl(reg32, gpiobase + GP_IO_SEL2);
-	}
-
-	/* Drive the output low */
-	reg32 = inl(gpiobase + GP_LVL2);
-	reg32 &= ~(1 << 28);
-	outl(reg32, gpiobase + GP_LVL2);
+	if (CONFIG_DRAM_RESET_GATE_GPIO >= 32)
+		southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32,
+						   gpiobase + GPIO_USE_SEL2,
+						   gpiobase + GP_IO_SEL2,
+						   gpiobase + GP_LVL2);
+	else
+		southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO,
+						   gpiobase + GPIO_USE_SEL,
+						   gpiobase + GP_IO_SEL,
+						   gpiobase + GP_LVL);
 }
 
 static void xhci_sleep(u8 slp_typ)