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authorPaul Menzel <paulepanter@users.sourceforge.net>2016-12-29 22:54:02 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-01-04 00:27:51 +0100
commit6c20b65849aeda664cc40ebc0f0bab2e99768423 (patch)
treee09bf7dbb67b69d46cb36444a7dc08e923053e5b /src
parent68fdb785b2183cfa3312266b4a800174ba2d64e5 (diff)
downloadcoreboot-6c20b65849aeda664cc40ebc0f0bab2e99768423.tar.xz
intel/i945 boards: Add romstage time stamps
Currently, some Intel 945 boards miss some or all of the time stamps *1:start of rom stage*, *2:before ram initialization*, and *3:after ram initialization*, so add them. Use the same formatting as used for the board Lenovo X60, which already has code for all the time stamps. Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17993 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/asus/p5gc-mx/romstage.c7
-rw-r--r--src/mainboard/getac/p470/romstage.c2
-rw-r--r--src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c8
-rw-r--r--src/mainboard/ibase/mb899/romstage.c6
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c7
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c7
-rw-r--r--src/mainboard/roda/rk886ex/romstage.c7
7 files changed, 44 insertions, 0 deletions
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 8785595da4..f0c48a3700 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -26,6 +26,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
+#include <timestamp.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <pc80/mc146818rtc.h>
@@ -216,6 +217,9 @@ void mainboard_romstage_entry(unsigned long bist)
u8 m_bsel;
u8 c_bsel = msr_get_fsb();
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (bist == 0)
enable_lapic();
@@ -252,7 +256,10 @@ void mainboard_romstage_entry(unsigned long bist)
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
+
+ timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
+ timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index db675dccdf..20130f27d2 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -306,7 +306,9 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif
+ timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : 0, NULL);
+ timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index d84eae1d93..62729a742c 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -25,6 +25,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
+#include <timestamp.h>
#include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h>
#include <pc80/mc146818rtc.h>
@@ -165,6 +166,10 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0, boot_mode = 0;
+
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (bist == 0)
enable_lapic();
@@ -200,7 +205,10 @@ void mainboard_romstage_entry(unsigned long bist)
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
dump_spd_registers();
#endif
+
+ timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
+ timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 2a8965ebcb..dedbd55358 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -24,6 +24,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
+#include <timestamp.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include <pc80/mc146818rtc.h>
@@ -222,6 +223,9 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (bist == 0)
enable_lapic();
@@ -254,7 +258,9 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif
+ timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : 0, NULL);
+ timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 8077ba212d..414b7056ed 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -24,6 +24,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
+#include <timestamp.h>
#include <superio/smsc/lpc47m15x/lpc47m15x.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
@@ -154,6 +155,10 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0, boot_mode = 0;
+
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (bist == 0)
enable_lapic();
@@ -187,7 +192,9 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif
+ timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
+ timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index be51b7a3b2..e5fdc7318f 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -20,6 +20,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
+#include <timestamp.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
@@ -324,6 +325,10 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
+
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (bist == 0)
enable_lapic();
@@ -361,7 +366,9 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif
+ timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : 0, NULL);
+ timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 3d6ae19fac..eef3ff9532 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -25,6 +25,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
+#include <timestamp.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
@@ -245,6 +246,10 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
+
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (bist == 0)
enable_lapic();
@@ -285,7 +290,9 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif
+ timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : 0, NULL);
+ timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();