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| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2015-07-15 13:47:33 -0500 |
|---|---|---|
| committer | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2015-08-09 21:16:41 +0200 |
| commit | 6f0e8bdc169e152a8065694c5ef69f0a654d9f31 (patch) | |
| tree | 8d187ec3f10def0506be034caf715f423e0ea2a7 /src | |
| parent | 0dee57837b213c4c3f61feecb24a98bcb9b0fb85 (diff) | |
| download | coreboot-6f0e8bdc169e152a8065694c5ef69f0a654d9f31.tar.xz | |
amd8111, ck804, mcp55: use CONFIG_HPET_ADDRESS
As acpi_write_hpet() uses CONFIG_HPET_ADDRESS in the HPET table we
need to use CONFIG_HPET_ADDRESS when assigning it to the device.
Change-Id: I656f917658f1c1717bb3653fa048a6d36fca2454
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10925
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/amd/amd8111/lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/lpc.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index df3eff4f51..8841760c02 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -26,7 +26,7 @@ static void enable_hpet(struct device *dev) { unsigned long hpet_address; - pci_write_config32(dev,0xa0, 0xfed00001); + pci_write_config32(dev, 0xa0, CONFIG_HPET_ADDRESS|1); hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe; printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index d0f687f16b..be8a39c258 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -207,7 +207,7 @@ static void ck804_lpc_read_resources(device_t dev) res = find_resource(dev, 0x44); /* HPET */ if (res) { - res->base = 0xfed00000; + res->base = CONFIG_HPET_ADDRESS; res->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } } diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 8d1a83a244..5726c76293 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -83,7 +83,7 @@ static void enable_hpet(struct device *dev) { unsigned long hpet_address; - pci_write_config32(dev, 0x44, 0xfed00001); + pci_write_config32(dev, 0x44, CONFIG_HPET_ADDRESS|1); hpet_address=pci_read_config32(dev, 0x44) & 0xfffffffe; printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } |