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authorAaron Durbin <adurbin@chromium.org>2020-07-02 11:08:21 -0600
committerAaron Durbin <adurbin@chromium.org>2020-07-03 15:36:30 +0000
commit76fcf82901af76cd70bdac7fbfddf58f41770d0a (patch)
tree4dd1fbbeb0333631b2722bb45ed707824e273396 /src
parentd3758540a951510ede21ebb76cbc196ae8ed0e68 (diff)
downloadcoreboot-76fcf82901af76cd70bdac7fbfddf58f41770d0a.tar.xz
mb/google/zork: adjust eSPI virtual irq settings
The eSPI polarity macros were reversed. Those are fixed so adjust the corresponding values related to the correct expectations of the IRQ path: eSPI virtual wire IRQs are active level high. The EC sends active level high virtual wire IRQs. The default interrupt encodings in ACPI for P2/S devices are active edge high. Therefore, there is no need to override anything. BUG=b:157984427 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia28d82cd9e432df98839f68bac4eae4447455e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree.cb10
-rw-r--r--src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h2
2 files changed, 1 insertions, 11 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb
index 93247492ed..85ce4e6795 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb
@@ -103,19 +103,11 @@ chip soc/amd/picasso
.oob_ch_en = 0,
.flash_ch_en = 0,
- .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12),
+ .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
}"
register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
- register "irq_override" = "{
- /* PS/2 keyboard IRQ1 override */
- {1, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH},
-
- /* PS/2 mouse IRQ12 override */
- {12, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH},
- }"
-
device cpu_cluster 0 on
device lapic 0 on end
end
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
index 8ef0645afd..ff42989286 100644
--- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h
@@ -59,8 +59,6 @@
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
-#define SIO_EC_PS2K_IRQ IRQ (Level, ActiveHigh, Exclusive) {1}
-#define SIO_EC_PS2M_IRQ IRQ (Level, ActiveHigh, Exclusive) {12}
/*
* Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in