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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-06 19:00:31 +0200 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-09 21:29:53 +0000 |
commit | 7cdcc38f292d7a8ffd285d17c848e60e41eec759 (patch) | |
tree | 13bba3b16f89d74367fdc043e10d707534a24525 /src | |
parent | c528426b264c897b6c17ef14846afea3711042cb (diff) | |
download | coreboot-7cdcc38f292d7a8ffd285d17c848e60e41eec759.tar.xz |
sb/intel/common: Add smbus_host_reset()
Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/include/device/smbus_host.h | 5 | ||||
-rw-r--r-- | src/southbridge/intel/bd82x6x/early_smbus.c | 7 | ||||
-rw-r--r-- | src/southbridge/intel/common/smbus.c | 9 | ||||
-rw-r--r-- | src/southbridge/intel/i82371eb/early_smbus.c | 8 | ||||
-rw-r--r-- | src/southbridge/intel/i82801dx/early_smbus.c | 11 | ||||
-rw-r--r-- | src/southbridge/intel/i82801gx/early_smbus.c | 7 | ||||
-rw-r--r-- | src/southbridge/intel/i82801ix/early_smbus.c | 7 | ||||
-rw-r--r-- | src/southbridge/intel/i82801jx/early_smbus.c | 7 | ||||
-rw-r--r-- | src/southbridge/intel/ibexpeak/early_smbus.c | 7 | ||||
-rw-r--r-- | src/southbridge/intel/lynxpoint/early_smbus.c | 7 |
10 files changed, 28 insertions, 47 deletions
diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index 2aa160ffbd..071eef0ff2 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -32,4 +32,9 @@ int do_smbus_block_write(uintptr_t base, u8 device, u8 cmd, size_t bytes, const int do_i2c_eeprom_read(uintptr_t base, u8 device, u8 offset, size_t bytes, u8 *buf); int do_i2c_block_write(uintptr_t base, u8 device, size_t bytes, u8 *buf); +/* Upstream API */ + +void smbus_host_reset(uintptr_t base); + + #endif diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 61625ccdf3..5ecce284d6 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -14,11 +14,9 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "pch.h" @@ -44,11 +42,8 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE); - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index f294f3163b..f6805ad50f 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -92,6 +92,15 @@ static void host_and_or(uintptr_t base, u8 reg, u8 mask, u8 or) host_outb(base, reg, value); } +void smbus_host_reset(uintptr_t base) +{ + /* Disable interrupt generation. */ + host_outb(base, SMBHSTCTL, 0); + + /* Clear any lingering errors, so transactions can run. */ + host_and_or(base, SMBHSTSTAT, 0xff, 0); +} + static int host_completed(u8 status) { if (status & SMBHSTSTS_HOST_BUSY) diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 4168a057ef..917a3b45f1 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -15,12 +15,11 @@ */ #include <stdint.h> -#include <arch/io.h> +#include <console/console.h> #include <device/pci_ops.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "i82371eb.h" @@ -47,8 +46,9 @@ void enable_smbus(void) reg16 |= PCI_COMMAND_IO; pci_write_config16(dev, PCI_COMMAND, reg16); - /* Clear any lingering errors, so the transaction will run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + smbus_host_reset(SMBUS_IO_BASE); + + printk(BIOS_DEBUG, "SMBus controller enabled\n"); } int smbus_read_byte(u8 device, u8 address) diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 5e82ded6be..77b0aa084b 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -14,11 +14,9 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "i82801dx.h" @@ -27,17 +25,16 @@ void enable_smbus(void) { pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ pci_write_config8(dev, 0x40, 0x01); /* Set smbus iospace enable */ pci_write_config16(dev, 0x4, 0x01); - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + smbus_host_reset(SMBUS_IO_BASE); + + printk(BIOS_DEBUG, "SMBus controller enabled\n"); } int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 49056eba83..60fccebc64 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -14,11 +14,9 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "i82801gx.h" @@ -43,11 +41,8 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE); - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index e067733a55..4286760a7e 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -15,12 +15,10 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "i82801ix.h" @@ -45,11 +43,8 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE); - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index f841355f1a..594400f710 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -15,11 +15,9 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "i82801jx.h" @@ -40,11 +38,8 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE); - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 0d18ed0b7c..fdf0c329f3 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -14,11 +14,9 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "pch.h" @@ -44,11 +42,8 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE); - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 61625ccdf3..5ecce284d6 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -14,11 +14,9 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "pch.h" @@ -44,11 +42,8 @@ void enable_smbus(void) /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE); - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); } |