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authorAaron Durbin <adurbin@chromium.org>2020-04-11 10:06:37 -0600
committerAaron Durbin <adurbin@chromium.org>2020-05-01 23:28:37 +0000
commit806ea463dbc20c9a577923af51e9976baaf6790a (patch)
treee6f16749a1665aeeec900b1e0018fb6d34e77307 /src
parent00a220877c8fc27f161017e68b67fce23117c0ad (diff)
downloadcoreboot-806ea463dbc20c9a577923af51e9976baaf6790a.tar.xz
soc/amd/picasso: add sd/emmc0 configuration to chip.h
In order to isolate mainboard code from direct FSPS manipulation allow sd/emmc0 configuration to be supplied by devicetree.cb. BUG=b:153502861 Change-Id: I2569ccccd638faaf2c9ac68fe582ecb9fa967d9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Commit-Queue: Aaron Durbin <adurbin@google.com> Tested-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/picasso/chip.h15
-rw-r--r--src/soc/amd/picasso/fsp_params.c52
-rw-r--r--src/soc/amd/picasso/include/soc/platform_descriptors.h15
3 files changed, 82 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index edb1b69bb0..7c6823239c 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -86,6 +86,21 @@ struct soc_amd_picasso_config {
enum spi100_speed spi_fast_speed;
enum spi100_speed spi_altio_speed;
enum spi100_speed spi_tpm_speed;
+
+ enum {
+ SD_EMMC_DISABLE,
+ SD_EMMC_SD_LOW_SPEED,
+ SD_EMMC_SD_HIGH_SPEED,
+ SD_EMMC_SD_UHS_I_SDR_50,
+ SD_EMMC_SD_UHS_I_DDR_50,
+ SD_EMMC_SD_UHS_I_SDR_104,
+ SD_EMMC_EMMC_SDR_26,
+ SD_EMMC_EMMC_SDR_52,
+ SD_EMMC_EMMC_DDR_52,
+ SD_EMMC_EMMC_HS200,
+ SD_EMMC_EMMC_HS400,
+ SD_EMMC_EMMC_HS300,
+ } sd_emmc_config;
};
typedef struct soc_amd_picasso_config config_t;
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 0dbda093f3..d11dae201c 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -7,6 +7,55 @@
#include <fsp/api.h>
#include "chip.h"
+static void fsps_update_emmc_config(FSP_S_CONFIG *scfg,
+ const struct soc_amd_picasso_config *cfg)
+{
+ int val = SD_DISABLE;
+
+ switch (cfg->sd_emmc_config) {
+ case SD_EMMC_DISABLE:
+ val = SD_DISABLE;
+ break;
+ case SD_EMMC_SD_LOW_SPEED:
+ val = SD_LOW_SPEED;
+ break;
+ case SD_EMMC_SD_HIGH_SPEED:
+ val = SD_HIGH_SPEED;
+ break;
+ case SD_EMMC_SD_UHS_I_SDR_50:
+ val = SD_UHS_I_SDR_50;
+ break;
+ case SD_EMMC_SD_UHS_I_DDR_50:
+ val = SD_UHS_I_DDR_50;
+ break;
+ case SD_EMMC_SD_UHS_I_SDR_104:
+ val = SD_UHS_I_SDR_104;
+ break;
+ case SD_EMMC_EMMC_SDR_26:
+ val = EMMC_SDR_26;
+ break;
+ case SD_EMMC_EMMC_SDR_52:
+ val = EMMC_SDR_52;
+ break;
+ case SD_EMMC_EMMC_DDR_52:
+ val = EMMC_DDR_52;
+ break;
+ case SD_EMMC_EMMC_HS200:
+ val = EMMC_HS200;
+ break;
+ case SD_EMMC_EMMC_HS400:
+ val = EMMC_HS400;
+ break;
+ case SD_EMMC_EMMC_HS300:
+ val = EMMC_HS300;
+ break;
+ default:
+ break;
+ }
+
+ scfg->emmc0_mode = val;
+}
+
static void fill_pcie_descriptors(FSP_S_CONFIG *scfg,
const picasso_fsp_pcie_descriptor *descs, size_t num)
{
@@ -49,7 +98,10 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg)
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
+ const struct soc_amd_picasso_config *cfg;
FSP_S_CONFIG *scfg = &supd->FspsConfig;
+ cfg = config_of_soc();
+ fsps_update_emmc_config(scfg, cfg);
fsp_fill_pcie_ddi_descriptors(scfg);
}
diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h
index bc67550fd0..7a8444b062 100644
--- a/src/soc/amd/picasso/include/soc/platform_descriptors.h
+++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h
@@ -8,6 +8,21 @@
#include <platform_descriptors.h>
#include <FspsUpd.h>
+/* These tempory macros apply to emmc0_mode field in FSP_S_CONFIG.
+ * TODO: Remove when official definitions arrive. */
+#define SD_DISABLE 0
+#define SD_LOW_SPEED 1
+#define SD_HIGH_SPEED 2
+#define SD_UHS_I_SDR_50 3
+#define SD_UHS_I_DDR_50 4
+#define SD_UHS_I_SDR_104 5
+#define EMMC_SDR_26 6
+#define EMMC_SDR_52 7
+#define EMMC_DDR_52 8
+#define EMMC_HS200 9
+#define EMMC_HS400 10
+#define EMMC_HS300 11
+
/* Mainboard callback to obtain PCIe and DDI descriptors. */
void mainboard_get_pcie_ddi_descriptors(
const picasso_fsp_pcie_descriptor **pcie_descs, size_t *pcie_num,