diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-23 17:46:11 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-24 06:17:58 +0000 |
| commit | 80835a10e150d671dba4e4ea75b50dbd0521c4f5 (patch) | |
| tree | d7ea509a330c0f0c73b38ce47981c0ba1f4f9c4a /src | |
| parent | 32be9f90452d2bff25db7b745405ccb3f1bd811a (diff) | |
| download | coreboot-80835a10e150d671dba4e4ea75b50dbd0521c4f5.tar.xz | |
soc/intel/alderlake/romstage: Fix compilation issue
Refer to commit 490546f (soc/intel: rename get_prmrr_size) for details.
Change-Id: I4a83feedcdb337ba9613a07215196bc223fb46d1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45651
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 55980a8790..83c84ac518 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -53,7 +53,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, sizeof(config->PcieClkSrcClkReq)); - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; |