diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-04-27 23:05:52 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-04-29 19:49:09 +0200 |
| commit | 80a3df260767a6d9ad34b61572d483579c21476c (patch) | |
| tree | c4bd3b49f9dbf21d437b28a99b99b23b4e963d1b /src | |
| parent | 588ccaa9a7d94da4f5a5b3579eb9e3d06c9f4a51 (diff) | |
| download | coreboot-80a3df260767a6d9ad34b61572d483579c21476c.tar.xz | |
soc/intel/apollolake: clarify Fast SPI CS2 pad configuration
The pad for CS2 of the Fast SPI interface needs to be configured for
automatic MMIO translation when a SPI TPM is utilized. Instead of
unconditionally configuring that pad under LPC_TPM provide a explicit
Kconfig for a mainboard to select.
Change-Id: Ia94b90e12d71a4b849359188a853f7e036cc583b
Signed-off-by: Aaron Durbin <adurbin@chormium.org>
Reviewed-on: https://review.coreboot.org/14531
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/amenia/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 2 |
3 files changed, 10 insertions, 1 deletions
diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index be98b86d00..b2c1a8ce19 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select TPM_ON_FAST_SPI config CHROMEOS bool diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 7cd548b0a1..bdb8eeb75d 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -41,6 +41,14 @@ config CPU_SPECIFIC_OPTIONS select HAVE_HARD_RESET select SOC_INTEL_COMMON +config TPM_ON_FAST_SPI + bool + default n + select LPC_TPM + help + TPM part is conntected on Fast SPI interface, but the LPC MMIO + TPM transactions are decoded and serialized over the SPI interface. + config SOC_INTEL_COMMON_RESET bool default y diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 245645518a..abb713e708 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -102,7 +102,7 @@ void bootblock_soc_early_init(void) if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) soc_console_uart_init(); - if (IS_ENABLED(CONFIG_LPC_TPM)) + if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI)) tpm_enable(); if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC)) |