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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 10:00:28 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-22 10:49:18 +0200 |
| commit | 8431fcb8c8e248d777723e0a6651b9030d29cf8e (patch) | |
| tree | c9b06b7c67c8f6fa54d5ae03c59887ada4f0c690 /src | |
| parent | b4f827d45a08d849df9d15abd644e3a98a6f1932 (diff) | |
| download | coreboot-8431fcb8c8e248d777723e0a6651b9030d29cf8e.tar.xz | |
intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I616143b55d7c5726dc2475434e3fcb08b8d69bda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15230
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/model_2065x/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 10 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x201/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/packardbell/ms2290/romstage.c | 5 |
4 files changed, 13 insertions, 7 deletions
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index a13f5df26d..cdf9fed3e2 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -20,3 +20,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc +romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 269fbeffc7..51af5c69d2 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -170,7 +170,12 @@ clear_var_mtrrs: before_romstage: post_code(0x29) /* Call romstage.c main function. */ - call main + call romstage_main + + /* Save return value from romstage_main. It contains the stack to use + * after cache-as-ram is torn down. + */ + movl %eax, %ebx post_code(0x2f) @@ -272,7 +277,8 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl $CONFIG_RAMTOP, %esp + /* Setup stack as indicated by return value from romstage_main(). */ + movl %ebx, %esp movl %esp, %ebp call copy_and_run diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 53032f63ae..19b49094fb 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -28,6 +28,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> #include <ec/acpi/ec.h> #include <delay.h> #include <timestamp.h> @@ -174,8 +175,7 @@ static void set_fsb_frequency(void) smbus_block_write(0x69, 0, 5, block); } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { u32 reg32; int s3resume = 0; diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index e8f625d97a..d46a768f4b 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -28,12 +28,12 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> #include <ec/acpi/ec.h> #include <delay.h> #include <timestamp.h> #include <arch/acpi.h> #include <cbmem.h> -#include <cpu/intel/romstage.h> #include "arch/early_variables.h" #include <southbridge/intel/ibexpeak/pch.h> @@ -166,8 +166,7 @@ static inline u16 read_acpi16(u32 addr) } #endif -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { u32 reg32; int s3resume = 0; |