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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-06-26 17:46:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-07-12 15:17:31 +0200 |
| commit | 89186b2eb8167b56bf76d9cc03587d678b9bc661 (patch) | |
| tree | 8ff8e20b9e71eb37799e34cdb39761fb0b2e3011 /src | |
| parent | 74bb41275326cd34046454ab5a06bd7a17d5f887 (diff) | |
| download | coreboot-89186b2eb8167b56bf76d9cc03587d678b9bc661.tar.xz | |
SPD: Add CAS latency 2
CAS latency = 2 support added for DDR2.
Change-Id: I08d72a61c27ff0eab19e500a2f547a5e946de2f0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15439
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/spd.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/spd.h b/src/include/spd.h index 6424d33235..0bc7898749 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -147,6 +147,7 @@ enum spd_memory_type { #define SPD_CAS_LATENCY_3_5 0x20 #define SPD_CAS_LATENCY_4_0 0x40 +#define SPD_CAS_LATENCY_DDR2_2 (1 << 2) #define SPD_CAS_LATENCY_DDR2_3 (1 << 3) #define SPD_CAS_LATENCY_DDR2_4 (1 << 4) #define SPD_CAS_LATENCY_DDR2_5 (1 << 5) |