diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2017-06-25 20:41:40 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-06-27 02:15:56 +0000 |
| commit | 8bd88341e8c07df7b5640e15fa69acc115436d36 (patch) | |
| tree | f67ba52a56b4687910ac529dd1f3ef31433e1310 /src | |
| parent | d4b6ac19b0a6619ebe645875282643cc50cf7a3e (diff) | |
| download | coreboot-8bd88341e8c07df7b5640e15fa69acc115436d36.tar.xz | |
soc/intel/skylake: storage: Use word access for power state registers
In the D0 and D3 ACPI methods use word access to the PME status and
control register. This brings the code inline with the Intel reference
code and matches how the kernel handles access to this register.
BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<>D3 transition across multiple devices
Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/acpi/scs.asl | 36 |
1 files changed, 17 insertions, 19 deletions
diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index c2f50cce9b..60c546b045 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -21,12 +21,13 @@ Device (EMMC) Name (_ADR, 0x001E0004) Name (_DDN, "eMMC Controller") Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D")) + Name (TEMP, 0) OperationRegion (EMCR, PCI_Config, 0x00, 0x100) - Field (EMCR, DWordAcc, NoLock, Preserve) + Field (EMCR, WordAcc, NoLock, Preserve) { Offset (0x84), /* PMECTRLSTATUS */ - D0D3, 2, /* POWERSTATE */ + PMCR, 16, Offset (0xa2), /* PG_CONFIG */ , 2, PGEN, 1, /* PG_ENABLE */ @@ -88,9 +89,8 @@ Device (EMMC) Sleep (2) /* Set Power State to D0 */ - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + And (PMCR, 0xFFFC, PMCR) + Store (PMCR, ^TEMP) } Method (_PS3, 0, Serialized) @@ -98,10 +98,9 @@ Device (EMMC) /* Enable Power Gate */ Store (1, ^PGEN) - /* Set Power State to D0 */ - Store (3, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + /* Set Power State to D3 */ + Or (PMCR, 0x0003, PMCR) + Store (PMCR, ^TEMP) } } @@ -110,12 +109,13 @@ Device (SDXC) { Name (_ADR, 0x001E0006) Name (_DDN, "SD Controller") + Name (TEMP, 0) OperationRegion (SDCR, PCI_Config, 0x00, 0x100) - Field (SDCR, DWordAcc, NoLock, Preserve) + Field (SDCR, WordAcc, NoLock, Preserve) { Offset (0x84), /* PMECTRLSTATUS */ - D0D3, 2, /* POWERSTATE */ + PMCR, 16, Offset (0xa2), /* PG_CONFIG */ , 2, PGEN, 1, /* PG_ENABLE */ @@ -138,14 +138,13 @@ Device (SDXC) ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A) Sleep (2) - /* Set bits 31, 6, 2, 0 */ + /* Set bits 8, 7, 2, 0 */ ^^PCRO (PID_SCS, 0x600, 0x00000185) Sleep (2) /* Set Power State to D0 */ - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + And (PMCR, 0xFFFC, PMCR) + Store (PMCR, ^TEMP) } Method (_PS3, 0, Serialized) @@ -153,10 +152,9 @@ Device (SDXC) /* Enable Power Gate */ Store (1, ^PGEN) - /* Set Power State to D0 */ - Store (3, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + /* Set Power State to D3 */ + Or (PMCR, 0x0003, PMCR) + Store (PMCR, ^TEMP) /* Enable 20K pull-down on CLK, CMD and DAT lines */ ^^PCRO (PID_GPIOCOM3, 0x4c4, 0x00001000) |