diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-06-04 10:10:31 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-05 15:51:40 +0000 |
| commit | 925ea51e4c9b04b84aa35a44644f4a123bc9a3ee (patch) | |
| tree | 9fa3cde57dc559123b56bd0de9b780cc94eb01bb /src | |
| parent | ce23d4c6f179358bf84cbdfa678d0435ae3b4cbe (diff) | |
| download | coreboot-925ea51e4c9b04b84aa35a44644f4a123bc9a3ee.tar.xz | |
soc/intel/cannonlake: Add option to skip coreboot MP init
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for CNL.
Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
6 files changed, 7 insertions, 6 deletions
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index 512354ed8f..6f70dfba2a 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" - register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index 4076ea6035..7d89b78e8b 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -29,7 +29,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 18aa65d890..d5d806c91e 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -6,7 +6,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" - register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 8bcb850f15..4c62800483 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -6,7 +6,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" - register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 0c4232c277..924764a6c8 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -295,7 +295,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Heci3Enabled = config->Heci3Enabled; params->Device4Enable = config->Device4Enable; - params->SkipMpInit = config->FspSkipMpInit; + params->SkipMpInit = !config->use_fsp_mp_init; /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 8fdb9646b3..d943f9c781 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -206,7 +206,12 @@ struct soc_intel_cannonlake_config { CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ } chipset_lockdown; - uint8_t FspSkipMpInit; + /* + * Option for mainboard to skip coreboot MP initialization + * 0 = Make use of coreboot MP Init + * 1 = Make use of FSP MP Init + */ + uint8_t use_fsp_mp_init; /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ |