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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-20 10:49:38 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-26 07:09:24 +0200 |
| commit | 9551bed306aa54f5a707bde1d2a934a5341411b8 (patch) | |
| tree | b0196a18c38d2b2d193c1a00cda4db7294916908 /src | |
| parent | d950f5191d1f7a0bd3a495cb630deda647d4245c (diff) | |
| download | coreboot-9551bed306aa54f5a707bde1d2a934a5341411b8.tar.xz | |
intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
Match the definition and use of these variable with haswell, such that
DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE.
Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15761
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 11 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 32 |
2 files changed, 32 insertions, 11 deletions
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 1a1167c057..702881d19f 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -20,7 +20,11 @@ #include <arch/acpi.h> #include "northbridge/intel/sandybridge/sandybridge.h" -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +/* The full cache-as-ram size includes the cache-as-ram portion from coreboot + * and the space used by the reference code. These 2 values combined should + * be a power of 2 because the MTRR setup assumes that. */ +#define CACHE_AS_RAM_SIZE \ + (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE /* Cache 4GB - MRC_SIZE_KB for MRC */ @@ -159,9 +163,8 @@ clear_mtrrs: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - /* Set up the stack pointer below MRC variable space. */ - movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \ - CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp /* Restore the BIST result. */ diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index d3edf03a7d..2fb455159e 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -69,18 +69,35 @@ config MRC_CACHE_SIZE depends on !CHROMEOS default 0x10000 +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/sandybridge/bootblock.c" + +if USE_NATIVE_RAMINIT + config DCACHE_RAM_BASE hex - default 0xff7e0000 if !USE_NATIVE_RAMINIT - default 0xfefe0000 if USE_NATIVE_RAMINIT + default 0xfefe0000 config DCACHE_RAM_SIZE hex default 0x20000 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/sandybridge/bootblock.c" +config DCACHE_RAM_MRC_VAR_SIZE + hex + default 0x0 + +endif # USE_NATIVE_RAMINIT + +if !USE_NATIVE_RAMINIT + +config DCACHE_RAM_BASE + hex + default 0xff7e0000 + +config DCACHE_RAM_SIZE + hex + default 0x1c000 config DCACHE_RAM_MRC_VAR_SIZE hex @@ -88,7 +105,6 @@ config DCACHE_RAM_MRC_VAR_SIZE config MRC_FILE string "Intel System Agent path and filename" - depends on !USE_NATIVE_RAMINIT default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin" help The path and filename of the file to use as System Agent @@ -96,6 +112,8 @@ config MRC_FILE config MMCONF_BASE_ADDRESS hex - default 0xf0000000 if !USE_NATIVE_RAMINIT + default 0xf0000000 + +endif # !USE_NATIVE_RAMINIT endif |