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authorAngel Pons <th3fanbus@gmail.com>2020-10-25 12:23:45 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-03 19:12:01 +0000
commit96a480d507a97c27aa13a93ef9bc9176f498a895 (patch)
treee9d048cf205d3b936ed31819b8d11a6e14371397 /src
parent55a890fe3a4edede1580ab5c1d57dfe8e194e3f7 (diff)
downloadcoreboot-96a480d507a97c27aa13a93ef9bc9176f498a895.tar.xz
cpu/intel/haswell: Move smmrelocate.c MSR definitions to header
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: Ia271718477ea227b9ba7e836b0abe02264778129 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46733 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/haswell/haswell.h20
-rw-r--r--src/cpu/intel/haswell/smmrelocate.c16
2 files changed, 20 insertions, 16 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index e0e1e1cdd3..9349a3d654 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -76,6 +76,26 @@
#define MSR_CONFIG_TDP_CONTROL 0x64b
#define MSR_TURBO_ACTIVATION_RATIO 0x64c
+#define SMM_MCA_CAP_MSR 0x17d
+#define SMM_CPU_SVRSTR_BIT 57
+#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
+
+#define MSR_PRMRR_PHYS_BASE 0x1f4
+#define MSR_PRMRR_PHYS_MASK 0x1f5
+#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
+#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
+
+#define SMM_FEATURE_CONTROL_MSR 0x4e0
+#define SMM_CPU_SAVE_EN (1 << 1)
+
+/* SMM save state MSRs */
+#define SMBASE_MSR 0xc20
+#define IEDBASE_MSR 0xc22
+
+/* MTRR_CAP_MSR bit definitions */
+#define SMRR_SUPPORTED (1 << 11)
+#define PRMRR_SUPPORTED (1 << 12)
+
/* P-state configuration */
#define PSS_MAX_ENTRIES 8
#define PSS_RATIO_STEP 2
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
index 2fc20aab3d..9e3554f9e3 100644
--- a/src/cpu/intel/haswell/smmrelocate.c
+++ b/src/cpu/intel/haswell/smmrelocate.c
@@ -17,22 +17,6 @@
#include <smp/node.h>
#include "haswell.h"
-#define MSR_PRMRR_PHYS_BASE 0x1f4
-#define MSR_PRMRR_PHYS_MASK 0x1f5
-#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
-#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5
-#define SMM_MCA_CAP_MSR 0x17d
-#define SMM_CPU_SVRSTR_BIT 57
-#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
-#define SMM_FEATURE_CONTROL_MSR 0x4e0
-#define SMM_CPU_SAVE_EN (1 << 1)
-/* SMM save state MSRs */
-#define SMBASE_MSR 0xc20
-#define IEDBASE_MSR 0xc22
-
-#define SMRR_SUPPORTED (1 << 11)
-#define PRMRR_SUPPORTED (1 << 12)
-
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
struct smm_relocation_params *relo_params)