vc/amd/fsp/picasso: add logical to lane number in port descriptor struct

The lane numbers in the PCIe/DXIO descriptor are the logical and not the
physical ones, so add logical to the corresponding field names of the
fsp_pcie_descriptor struct.

Change-Id: I7037fed225119218e87593932815aff815e83ff8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 44 insertions, 44 deletions

diff --git a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
index 326bcaa0e7..3625554a42 100644
--- a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
+++ b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
@@ -8,8 +8,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
 	{ /* MXM */
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 8,
-		.end_lane = 15,
+		.start_logical_lane = 8,
+		.end_logical_lane = 15,
 		.device_number = 1,
 		.function_number = 1,
 		.link_aspm = ASPM_L1,
@@ -21,8 +21,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
 	{ /* SSD */
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 0,
-		.end_lane = 1,
+		.start_logical_lane = 0,
+		.end_logical_lane = 1,
 		.device_number = 1,
 		.function_number = 7,
 		.link_aspm = ASPM_L1,
@@ -34,8 +34,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
 	{ /* WLAN */
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 4,
-		.end_lane = 4,
+		.start_logical_lane = 4,
+		.end_logical_lane = 4,
 		.device_number = 1,
 		.function_number = 2,
 		.link_aspm = ASPM_L1,
@@ -47,8 +47,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
 	{ /* LAN */
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 5,
-		.end_lane = 5,
+		.start_logical_lane = 5,
+		.end_logical_lane = 5,
 		.device_number = 1,
 		.function_number = 3,
 		.link_aspm = ASPM_L1,
@@ -60,8 +60,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
 	{ /* WWAN */
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 6,
-		.end_lane = 6,
+		.start_logical_lane = 6,
+		.end_logical_lane = 6,
 		.device_number = 1,
 		.function_number = 4,
 		.link_aspm = ASPM_L1,
@@ -73,8 +73,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
 	{ /* WIFI */
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 7,
-		.end_lane = 7,
+		.start_logical_lane = 7,
+		.end_logical_lane = 7,
 		.gpio_group_id = 1,
 		.device_number = 1,
 		.function_number = 5,
@@ -87,8 +87,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
 	{ /* SATA EXPRESS */
 		.port_present = true,
 		.engine_type = SATA_ENGINE,
-		.start_lane = 2,
-		.end_lane = 3,
+		.start_logical_lane = 2,
+		.end_logical_lane = 3,
 		.gpio_group_id = 1,
 		.channel_type = SATA_CHANNEL_LONG,
 	}
@@ -98,8 +98,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
 	{ /* MXM */
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 8,
-		.end_lane = 11,
+		.start_logical_lane = 8,
+		.end_logical_lane = 11,
 		.device_number = 1,
 		.function_number = 1,
 		.link_aspm = ASPM_L1,
@@ -111,8 +111,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
 	{ /* SSD */
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 0,
-		.end_lane = 1,
+		.start_logical_lane = 0,
+		.end_logical_lane = 1,
 		.device_number = 1,
 		.function_number = 7,
 		.link_aspm = ASPM_L1,
@@ -124,8 +124,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
 	{ /* WLAN */
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 4,
-		.end_lane = 4,
+		.start_logical_lane = 4,
+		.end_logical_lane = 4,
 		.device_number = 1,
 		.function_number = 2,
 		.link_aspm = ASPM_L1,
@@ -137,8 +137,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
 	{ /* LAN */
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 5,
-		.end_lane = 5,
+		.start_logical_lane = 5,
+		.end_logical_lane = 5,
 		.device_number = 1,
 		.function_number = 3,
 		.link_aspm = ASPM_L1,
@@ -150,8 +150,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
 	{ /* SATA */
 		.port_present = true,
 		.engine_type = SATA_ENGINE,
-		.start_lane = 2,
-		.end_lane = 3,
+		.start_logical_lane = 2,
+		.end_logical_lane = 3,
 		.gpio_group_id = 1,
 		.channel_type = SATA_CHANNEL_LONG,
 	}
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
index b0037090c7..82a11b05fb 100644
--- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
@@ -18,8 +18,8 @@ static const fsp_pcie_descriptor pcie_descriptors[] = {
 		// NVME SSD
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = NVME_START_LANE,
-		.end_lane = NVME_END_LANE,
+		.start_logical_lane = NVME_START_LANE,
+		.end_logical_lane = NVME_END_LANE,
 		.device_number = 1,
 		.function_number = 7,
 		.link_aspm = ASPM_L1,
@@ -33,8 +33,8 @@ static const fsp_pcie_descriptor pcie_descriptors[] = {
 		// WLAN
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = WLAN_START_LANE,
-		.end_lane = WLAN_END_LANE,
+		.start_logical_lane = WLAN_START_LANE,
+		.end_logical_lane = WLAN_END_LANE,
 		.device_number = 1,
 		.function_number = 2,
 		.link_aspm = ASPM_L1,
@@ -48,8 +48,8 @@ static const fsp_pcie_descriptor pcie_descriptors[] = {
 		// SD Reader
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = SD_START_LANE,
-		.end_lane = SD_END_LANE,
+		.start_logical_lane = SD_START_LANE,
+		.end_logical_lane = SD_END_LANE,
 		.device_number = 1,
 		.function_number = 3,
 		.link_aspm = ASPM_L1,
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
index df42f6b87e..9e82684442 100644
--- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
@@ -23,8 +23,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
 		// NVME SSD
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 0,
-		.end_lane = 3,
+		.start_logical_lane = 0,
+		.end_logical_lane = 3,
 		.device_number = 1,
 		.function_number = 7,
 		.link_aspm = ASPM_L1,
@@ -37,8 +37,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
 		// WLAN
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 4,
-		.end_lane = 4,
+		.start_logical_lane = 4,
+		.end_logical_lane = 4,
 		.device_number = 1,
 		.function_number = 2,
 		.link_aspm = ASPM_L1,
@@ -52,8 +52,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
 		// SD Reader
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = 5,
-		.end_lane = 5,
+		.start_logical_lane = 5,
+		.end_logical_lane = 5,
 		.device_number = 1,
 		.function_number = 3,
 		.link_aspm = ASPM_L1,
@@ -69,8 +69,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
 		// NVME SSD
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = NVME_START_LANE,
-		.end_lane = NVME_END_LANE,
+		.start_logical_lane = NVME_START_LANE,
+		.end_logical_lane = NVME_END_LANE,
 		.device_number = 1,
 		.function_number = 7,
 		.link_aspm = ASPM_L1,
@@ -84,8 +84,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
 		// WLAN
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = WLAN_START_LANE,
-		.end_lane = WLAN_END_LANE,
+		.start_logical_lane = WLAN_START_LANE,
+		.end_logical_lane = WLAN_END_LANE,
 		.device_number = 1,
 		.function_number = 2,
 		.link_aspm = ASPM_L1,
@@ -99,8 +99,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
 		// SD Reader
 		.port_present = true,
 		.engine_type = PCIE_ENGINE,
-		.start_lane = SD_START_LANE,
-		.end_lane = SD_END_LANE,
+		.start_logical_lane = SD_START_LANE,
+		.end_logical_lane = SD_END_LANE,
 		.device_number = 1,
 		.function_number = 3,
 		.link_aspm = ASPM_L1,
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h
index 9765ea6f2e..acf821b6e2 100644
--- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h
+++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h
@@ -113,8 +113,8 @@ typedef struct __packed {
 /* Beware that the lane numbers in here are the logical and not the physical lane numbers! */
 typedef struct __packed {
 	uint8_t		engine_type;
-	uint8_t		start_lane;			// Start lane of the pci device
-	uint8_t		end_lane;			// End lane of the pci device
+	uint8_t		start_logical_lane;		// Start lane of the pci device
+	uint8_t		end_logical_lane;		// End lane of the pci device
 	uint8_t		gpio_group_id;			// FCH reset number. 0 is global reset
 	uint32_t	port_present		:1;	// Should be TRUE if train link
 	uint32_t	reserved_3		:7;