summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-01-10 14:52:53 +0100
committerPatrick Rudolph <siro@das-labor.org>2019-01-15 07:46:28 +0000
commita649310ea478bff8092301bdd6128f36771afb2b (patch)
treee1d0c41b5e37208283ffc9922e9ffa83ffff55cb /src
parent6085d39bdb2c23f91fdda752d96e37a57fef8f82 (diff)
downloadcoreboot-a649310ea478bff8092301bdd6128f36771afb2b.tar.xz
mainboard/ocp/wedge100s: Fix uart
* Route IO 0x6e/0x6f to LPC bus * Setup ITE8526 in early_mainboard_romstage_entry * Fix romstage serial console by disabling internal uart default setting * Unselect CONFIG_INTEGRATED_UART, as it doesn't use internal UARTs * Select CONFIG_DRIVERS_UART_8250IO, as it has a SuperIO serial * Configure UPDs related to serial Change-Id: I59cd83ed43dbf4ee26685e4a573de153291f7074 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/ocp/wedge100s/Kconfig7
-rw-r--r--src/mainboard/ocp/wedge100s/romstage.c34
2 files changed, 38 insertions, 3 deletions
diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig
index e850887fe3..ce9c097cca 100644
--- a/src/mainboard/ocp/wedge100s/Kconfig
+++ b/src/mainboard/ocp/wedge100s/Kconfig
@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
select ENABLE_FSP_FAST_BOOT
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1
+ select DRIVERS_UART_8250IO
config VBOOT
select VBOOT_VBNV_CMOS
@@ -45,9 +46,6 @@ config VIRTUAL_ROM_SIZE
hex
default 0x1000000
-config DRIVERS_UART_8250IO
- def_bool n
-
config FSP_PACKAGE_DEFAULT
bool "Configure defaults for the Intel FSP package"
default n
@@ -57,4 +55,7 @@ config FMDFILE
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro.fmd" if VBOOT
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
+config INTEGRATED_UART
+ def_bool n
+
endif # BOARD_OCP_WEDGE100S
diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c
index 9e294d978b..e14a09f5ef 100644
--- a/src/mainboard/ocp/wedge100s/romstage.c
+++ b/src/mainboard/ocp/wedge100s/romstage.c
@@ -20,6 +20,12 @@
#include <cpu/x86/msr.h>
#include <cf9_reset.h>
#include <console/console.h>
+#include <soc/pci_devs.h>
+#include <soc/lpc.h>
+#include <superio/ite/common/ite.h>
+
+#define SUPERIO_DEV 0x6e
+#define SERIAL_DEV PNP_DEV(SUPERIO_DEV, 1)
/**
* /brief mainboard call for setup that needs to be done before fsp init
@@ -27,6 +33,14 @@
*/
void early_mainboard_romstage_entry(void)
{
+ /* Decode 0x6e/0x6f on LPC bus (actually 0x6c-0x6f) */
+ pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC,
+ (0 << 16) | ALIGN_DOWN(SUPERIO_DEV, 4) | 1);
+
+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+
/*
* Sometimes the system boots in an invalid state, where random values
* have been written to MSRs and then the MSRs are locked.
@@ -60,5 +74,25 @@ void late_mainboard_romstage_entry(void)
*/
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
{
+ UPD_DATA_REGION *fsp_upd_data = FspRtBuffer->Common.UpdDataRgnPtr;
+ if (IS_ENABLED(CONFIG_FSP_USES_UPD)) {
+ /* The internal UART operates on 0x3f8/0x2f8.
+ * As it's not wired up and conflicts with SuperIO decoding
+ * the same range, make sure to disable it.
+ */
+ fsp_upd_data->SerialPortControllerInit0 = 0;
+ fsp_upd_data->SerialPortControllerInit1 = 0;
+
+ /* coreboot will initialize UART.
+ * No need for FSP to do it again.
+ */
+ fsp_upd_data->SerialPortConfigure = 0;
+ fsp_upd_data->SerialPortBaudRate = 0;
+ /* Make FSP use serial IO */
+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+ fsp_upd_data->SerialPortType = 1;
+ else
+ fsp_upd_data->SerialPortType = 0;
+ }
}