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authorPraveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>2019-10-29 14:47:11 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-10 20:42:14 +0000
commitaa6a8fb9198acfe22fec944bc9484a800d689ff4 (patch)
treea0bfa61c4d347cb97b019d2cc2de897990e81fb9 /src
parentb7731574f498dc8fd81c258b248ddfeda3eab5b5 (diff)
downloadcoreboot-aa6a8fb9198acfe22fec944bc9484a800d689ff4.tar.xz
mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config
Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64 Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36423 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/kunimitsu/devicetree.cb2
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 670a474865..ea3578550c 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -34,7 +34,7 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
register "HeciEnabled" = "0"
- register "SaGv" = "3"
+ register "SaGv" = "SaGv_Enabled"
register "PmTimerDisabled" = "1"
register "pirqa_routing" = "PCH_IRQ11"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 5d69e52740..c2dd6f97cf 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -42,7 +42,7 @@ chip soc/intel/skylake
register "Device4Enable" = "0"
register "Heci3Enabled" = "0"
- register "SaGv" = "3"
+ register "SaGv" = "SaGv_Enabled"
register "PmTimerDisabled" = "0"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch