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| author | Duncan Laurie <dlaurie@chromium.org> | 2015-02-24 10:51:04 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-18 08:53:08 +0200 |
| commit | ab7586fa264bfa6f31072c1a64142683dc68b98e (patch) | |
| tree | 0f3e51c8b679a72cb03244f33bfc3eca3b70d743 /src | |
| parent | aafdddfc3825580ecf1b73f0e423b5637e27e556 (diff) | |
| download | coreboot-ab7586fa264bfa6f31072c1a64142683dc68b98e.tar.xz | |
broadwell: Set C9/C10 vccmin
This is done via a PCODE mailbox write.
BUG=chrome-os-partner:37043
BRANCH=broadwell
TEST=build and boot on samus
Change-Id: I95e8fe3e28eec76d6b5b488a0c770c04f408700e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b90bef7f708b1ce83f6e124f4b38ae51ec6b0597
Original-Change-Id: I95cd4c17db672a53ba05f85ba5fa7bc866af1543
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/252862
Original-Reviewed-by: Alec Berg <alecaberg@chromium.org>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit ab6b4bddf3365713aa40d194c2dbd3e59985f00d)
Original-Reviewed-on: https://chromium-review.googlesource.com/252883
Reviewed-on: http://review.coreboot.org/9783
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/broadwell/cpu.c | 23 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/systemagent.h | 2 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 9073241e30..984ff7658a 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -178,6 +178,26 @@ static u32 pcode_mailbox_read(u32 command) return MCHBAR32(BIOS_MAILBOX_DATA); } +static int pcode_mailbox_write(u32 command, u32 data) +{ + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); + return -1; + } + + MCHBAR32(BIOS_MAILBOX_DATA) = data; + + /* Send command and start transaction */ + MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; + + if (pcode_ready() < 0) { + printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); + return -1; + } + + return 0; +} + static void initialize_vr_config(void) { device_t dev = SA_DEV_ROOT; @@ -238,6 +258,9 @@ static void initialize_vr_config(void) else msr.lo |= 0x006f; /* 1.60V */ wrmsr(MSR_VR_MISC_CONFIG2, msr); + + /* Set C9/C10 VCC Min */ + pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); } static void configure_pch_power_sharing(void) diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h index 5142b09e0a..325a4a5a6c 100644 --- a/src/soc/intel/broadwell/include/soc/systemagent.h +++ b/src/soc/intel/broadwell/include/soc/systemagent.h @@ -115,6 +115,8 @@ #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +#define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 +#define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 /* Errors are returned back in bits 7:0. */ #define MAILBOX_BIOS_ERROR_NONE 0 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 |