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authorBenjamin Doron <benjamin.doron00@gmail.com>2020-11-05 22:20:52 +0000
committerMichael Niewöhner <foss@mniewoehner.de>2020-11-09 21:34:42 +0000
commitac6565279ce30e2eed8e5fcc14f687013717c82f (patch)
treeaf980479dc647103e2e3d8493ff68c65be82d08a /src
parent136380fcac333ec28574f5bfb5b43b61a919130b (diff)
downloadcoreboot-ac6565279ce30e2eed8e5fcc14f687013717c82f.tar.xz
soc/intel/skylake: Enable PCH thermal depending on devicetree
Hook up PCH thermal subsystem configuration to devicetree. Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/protectli/vault_kbl/ramstage.c1
-rw-r--r--src/soc/intel/skylake/chip.c2
2 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c
index 962702fb5a..9518b1d721 100644
--- a/src/mainboard/protectli/vault_kbl/ramstage.c
+++ b/src/mainboard/protectli/vault_kbl/ramstage.c
@@ -13,7 +13,6 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params)
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
params->TurboMode = 1;
- params->PchThermalDeviceEnable = 0;
params->PchPort61hEnable = 1;
params->CdClock = 3;
}
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 89eaef5b56..1e13428252 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -295,6 +295,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev = pcidev_path_on_root(SA_DEVFN_TS);
params->Device4Enable = dev && dev->enabled;
+ dev = pcidev_path_on_root(PCH_DEVFN_THERMAL);
+ params->PchThermalDeviceEnable = dev && dev->enabled;
params->EnableTcoTimer = !config->PmTimerDisabled;
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;