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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-11-24 14:11:52 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-24 23:26:13 +0100 |
| commit | ad9a2bb0deeab41808a427e2f26420bd24ecb261 (patch) | |
| tree | a75c2ed650f9c9c7b4fadd4a61ca75aec28a8330 /src | |
| parent | 2d500ba59835828b0fe103159b41df58e3efe19e (diff) | |
| download | coreboot-ad9a2bb0deeab41808a427e2f26420bd24ecb261.tar.xz | |
nb/amd/mct_ddr3: Add additional verbose-level debug statements
Change-Id: Ie91c990d9c2bcab8292a75d87523a46d5694a34a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13146
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 10 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 2 |
2 files changed, 10 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 4cc87de5a8..22e9836757 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1428,8 +1428,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, if (check_antiphase == 0) { /* Check for early abort before analyzing per-nibble status */ - dword = Get_NB32_DCT(dev, dct, 0x264) & 0x1ffffff; - if (dword != 0) { + dword = Get_NB32_DCT(dev, dct, 0x264); + if ((dword & 0x1ffffff) != 0) { + print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 162 early abort: F2x264 ", dword, 6); dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 0; /* Fail */ continue; } @@ -1439,6 +1440,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, * Record pass / fail status */ dword = Get_NB32_DCT(dev, dct, 0x268) & 0x3ffff; + print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 163 read results: F2x268 ", dword, 6); if (dword & (0x3 << (lane * 2))) dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 0; /* Fail */ else @@ -1737,6 +1739,10 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc_D_Fam15 Receiver %d lane %d initial phy delay %04x: iterating from %04x to %04x\n", Receiver, lane, initial_phy_phase_delay[lane], rx_en_offset, 0x3ff); #endif for (current_phy_phase_delay[lane] = rx_en_offset; current_phy_phase_delay[lane] < 0x3ff; current_phy_phase_delay[lane] += ren_step) { +#if DQS_TRAIN_DEBUG > 0 + printk(BIOS_DEBUG, "%s: Receiver %d lane %d current phy delay: %04x\n", __func__, Receiver, lane, current_phy_phase_delay[lane]); +#endif + /* 2.10.5.8.3 (4 A) */ write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 1c756ab262..d316d27ea4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -228,6 +228,8 @@ static uint16_t fam15_receiver_enable_training_seed(struct DCTStatStruc *pDCTsta } } + printk(BIOS_DEBUG, "%s: using seed: %04x\n", __func__, seed); + return seed; } |