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authorErin Lo <erin.lo@mediatek.com>2019-03-11 14:54:21 +0800
committerJulius Werner <jwerner@chromium.org>2019-07-22 21:25:42 +0000
commitb1a2b22d8b904ea9bc5e7038fe2c2b3c1df8c1b2 (patch)
treede201816538e4c250d009942480023d4a53d045c /src
parentea61c0ee98e7fde76eac47ae02bce4d0dd8a971d (diff)
downloadcoreboot-b1a2b22d8b904ea9bc5e7038fe2c2b3c1df8c1b2.tar.xz
soc/mediatek/mt8183: Support SSPM
SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. BUG=b:80501386 BRANCH=none Test=Build pass Change-Id: I4ae6034454326f5115cd3948819adc448b67fb1c Signed-off-by: Erin Lo <erin.lo@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31516 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/mediatek/mt8183/Makefile.inc1
-rw-r--r--src/soc/mediatek/mt8183/include/soc/addressmap.h2
-rw-r--r--src/soc/mediatek/mt8183/include/soc/sspm.h27
-rw-r--r--src/soc/mediatek/mt8183/sspm.c42
4 files changed, 72 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index d35a07ed59..0a79ed7b98 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -49,6 +49,7 @@ ramstage-y += ../common/pmic_wrap.c
ramstage-y += ../common/rtc.c rtc.c
ramstage-y += soc.c
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+ramstage-y += sspm.c
ramstage-y += ../common/timer.c
ramstage-y += ../common/uart.c
ramstage-y += ../common/usb.c
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index e9f80d1607..0f085b2c8d 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -34,6 +34,8 @@ enum {
EMI_BASE = IO_PHYS + 0x00219000,
EMI_MPU_BASE = IO_PHYS + 0x00226000,
DRAMC_CH_BASE = IO_PHYS + 0x00228000,
+ SSPM_SRAM_BASE = IO_PHYS + 0x00400000,
+ SSPM_CFG_BASE = IO_PHYS + 0x00440000,
AUXADC_BASE = IO_PHYS + 0x01001000,
UART0_BASE = IO_PHYS + 0x01002000,
SPI0_BASE = IO_PHYS + 0x0100A000,
diff --git a/src/soc/mediatek/mt8183/include/soc/sspm.h b/src/soc/mediatek/mt8183/include/soc/sspm.h
new file mode 100644
index 0000000000..627088fdc7
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/sspm.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_SSPM_H
+#define SOC_MEDIATEK_MT8183_SSPM_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8183_sspm_regs {
+ u32 sw_rstn;
+};
+static struct mt8183_sspm_regs *const mt8183_sspm = (void *)SSPM_CFG_BASE;
+void sspm_init(void);
+#endif /* SOC_MEDIATEK_MT8183_SSPM_H */
diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c
new file mode 100644
index 0000000000..559034eacb
--- /dev/null
+++ b/src/soc/mediatek/mt8183/sspm.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/barrier.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <arch/mmio.h>
+#include <soc/sspm.h>
+#include <string.h>
+
+#define BUF_SIZE (64 * KiB)
+static uint8_t sspm_bin[BUF_SIZE] __aligned(8);
+
+void sspm_init(void)
+{
+ const char *file_name = "sspm.bin";
+ size_t fw_size = cbfs_boot_load_file(file_name,
+ sspm_bin,
+ sizeof(sspm_bin),
+ CBFS_TYPE_RAW);
+
+ if (fw_size == 0)
+ die("SSPM file :sspm.bin not found.");
+
+ memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size);
+ /* Memory barrier to ensure that all fw code is loaded
+ before we release the reset pin. */
+ mb();
+ write32(&mt8183_sspm->sw_rstn, 0x1);
+}