diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2017-01-13 12:45:19 +0530 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-01-16 04:46:21 +0100 |
| commit | b4a159706ec45c1f8e06b694c3531f94231097d6 (patch) | |
| tree | 2fc77d44b990212a4475815ebf3ec2c43adc7268 /src | |
| parent | 6f3a53b6f61126f05db950e1c0a2c0b4f1552e5f (diff) | |
| download | coreboot-b4a159706ec45c1f8e06b694c3531f94231097d6.tar.xz | |
mainboard/google/poppy: Update DQS and DQ Byte mappings for poppy
poppy schematics have undergone change after review, update
DQS and DQ Byte mappings based on the new schematics.
BUG=chrome-os-partner:61856
BRANCH=None
TEST= Build and boot all the poppy proto SKUs to OS.
Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18133
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/poppy/romstage.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 70e93d8e97..790e5ae833 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -25,14 +25,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; /* DQ byte map */ const u8 dq_map[2][12] = { - { 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0xF0, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0x33, 0xCC, 0x33, + { 0xCC, 0x33, 0x00, 0x33, 0xCC, 0x33, 0xCC, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { - { 0, 3, 1, 2, 4, 7, 6, 5 }, + { 2, 3, 1, 0, 4, 7, 6, 5 }, { 5, 6, 0, 3, 4, 7, 2, 1 }, }; /* Rcomp resistor */ |