diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-02-26 20:16:55 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-02-27 17:09:45 +0000 |
| commit | b7fb24677c4adff1d7648de260c3ee9e7f5b45ee (patch) | |
| tree | 3446cdb9c1d0e37d3656926f127598c10e177817 /src | |
| parent | dba6c4cfc08db8cb41b3f40d9ac9e03f92056046 (diff) | |
| download | coreboot-b7fb24677c4adff1d7648de260c3ee9e7f5b45ee.tar.xz | |
soc/intel/tigerlake: Add display related UPD configs for Jasper Lake
TEST=Build dedede board
Change-Id: I942a7036bf627b3d8262756e5e2026dcb0949dd5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39131
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params_jsl.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index e88d809cd3..829e1e35ea 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -87,6 +87,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + /* Display */ + m_cfg->DdiPortAConfig = config->DdiPortAConfig; + m_cfg->DdiPortBHpd = config->DdiPortBHpd; + m_cfg->DdiPortCHpd = config->DdiPortCHpd; + m_cfg->DdiPortBDdc = config->DdiPortBDdc; + m_cfg->DdiPortCDdc = config->DdiPortCDdc; + /* Audio */ m_cfg->PchHdaEnable = pcidev_path_on_root(PCH_DEVFN_HDA) ? dev->enabled : 0; |