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authorAngel Pons <th3fanbus@gmail.com>2020-07-07 03:03:43 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-08 22:09:56 +0000
commitbfc80098dad6a62c7cba0dd0043d46ad570e4e22 (patch)
tree07f4ac79dcb62162a23aa097f3292ab3856bdabf /src
parent4d962b2ecf25c82987a3456160c4566da34946d7 (diff)
downloadcoreboot-bfc80098dad6a62c7cba0dd0043d46ad570e4e22.tar.xz
nb/intel/pineview: Convert to ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: Ibc0988c4c86f7ffef8692ff3cf3ebd92235156b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43168 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/pineview/acpi/hostbridge.asl4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl
index 0a9897c69d..dae0b77e4e 100644
--- a/src/northbridge/intel/pineview/acpi/hostbridge.asl
+++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl
@@ -208,8 +208,8 @@ Method (_CRS, 0, Serialized)
* Enter actual TOLUD. The TOLUD register contains bits 27-31 of
* the top of memory address.
*/
- ShiftLeft (^MCHC.TLUD, 27, PMIN)
- Add(Subtract(PMAX, PMIN), 1, PLEN)
+ PMIN = ^MCHC.TLUD << 27
+ PLEN = PMAX - PMIN + 1
Return (MCRS)
}