diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-07-15 13:19:19 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-12 23:59:28 +0100 |
| commit | c20ff482a73ddb752fa32fa9d4b3e89420d1fee9 (patch) | |
| tree | 7567295a0f5212da9d431005b1a229ecdd394263 /src | |
| parent | bc3019cbd2081370ca0c556e10f923f0da6784d9 (diff) | |
| download | coreboot-c20ff482a73ddb752fa32fa9d4b3e89420d1fee9.tar.xz | |
storm: allow to override CBFS_SIZE configuration setting
The default CBFS size configuration setting is incorrect in case of
Qualcomm SOC targets, as the coreboot blob is much smaller than the
actual bootprom. Note that this size also must match the board fmap
defined in the appropriate depthcharge board directory.
BUG=chromium:394068
TEST=manual
. previously failing to boot coreboot image does not fail to load
depthcharge anymore.
Original-Change-Id: I1b178970b1deee05705490542e4a0c57500379dd
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208146
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 01f3561fdee7b5547534e20d423fbbb1b490532c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If573bbc6254cf6786e75970eae3ad2b327a7ecfe
Reviewed-on: http://review.coreboot.org/8640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/qualcomm/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/qualcomm/Kconfig b/src/soc/qualcomm/Kconfig index b7a12d4f9c..918093b7d8 100644 --- a/src/soc/qualcomm/Kconfig +++ b/src/soc/qualcomm/Kconfig @@ -1 +1,9 @@ source src/soc/qualcomm/ipq806x/Kconfig + +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default ROM_SIZE + help + CBFS size needs to match the size of memory allocated to the + coreboot blob elsewhere in the system. Make sure this config option + is fine tuned in the board config file. |