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authorMaggie Li <maggie.li@amd.com>2009-01-23 22:16:13 +0000
committerMarc Jones <marc.jones@amd.com>2009-01-23 22:16:13 +0000
commitcab81c03eb8a8ad04516571110aa5c0931499242 (patch)
tree614018ca2e4fc04a3d8130d292009562f7e2c4f2 /src
parent2e5481356f7e0f925dfe935e6d7a7f1cdd3681ec (diff)
downloadcoreboot-cab81c03eb8a8ad04516571110aa5c0931499242.tar.xz
Fix rs690 bug about GPPSB configuration.
Signed-off-by: Maggie Li <maggie.li@amd.com> Reviewed-by: Zheng Bao <Zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/amd/rs690/rs690_pcie.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c
index 5e80849d7f..9691e4ed18 100644
--- a/src/southbridge/amd/rs690/rs690_pcie.c
+++ b/src/southbridge/amd/rs690/rs690_pcie.c
@@ -133,8 +133,8 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
/* sets desired GPPSB configurations, bit4-7 */
reg = nbmisc_read_index(nb_dev, 0x67);
- reg &= 0xff0f; /* clean */
- reg |= cfg->gpp_configuration;
+ reg &= 0xffffff0f; /* clean */
+ reg |= cfg->gpp_configuration << 4;
nbmisc_write_index(nb_dev, 0x67, reg);
/* read bit14 and write back its inverst value */