mb/asus: Get rid of whitespace before tab

Change-Id: Id572144827b515e9e84c51aa3e4f8a20baf1c212
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

20 files changed, 102 insertions, 102 deletions

diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl
index 4d91b2a16c..94f83ecf08 100644
--- a/src/mainboard/asus/am1i-a/dsdt.asl
+++ b/src/mainboard/asus/am1i-a/dsdt.asl
@@ -45,7 +45,7 @@ DefinitionBlock (
 
 	/* System Bus */
 	Scope(\_SB) { /* Start \_SB scope */
-	 	/* global utility methods expected within the \_SB scope */
+		/* global utility methods expected within the \_SB scope */
 		#include <arch/x86/acpi/globutil.asl>
 
 		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
diff --git a/src/mainboard/asus/f2a85-m/acpi/gpe.asl b/src/mainboard/asus/f2a85-m/acpi/gpe.asl
index c34faaf05e..297db37a67 100644
--- a/src/mainboard/asus/f2a85-m/acpi/gpe.asl
+++ b/src/mainboard/asus/f2a85-m/acpi/gpe.asl
@@ -69,4 +69,4 @@ Scope(\_GPE) {	/* Start Scope GPE */
 		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
 		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 	}
-} 	/* End Scope GPE */
+}	/* End Scope GPE */
diff --git a/src/mainboard/asus/f2a85-m/acpi/sleep.asl b/src/mainboard/asus/f2a85-m/acpi/sleep.asl
index 3250f5ef4e..08b7de47f3 100644
--- a/src/mainboard/asus/f2a85-m/acpi/sleep.asl
+++ b/src/mainboard/asus/f2a85-m/acpi/sleep.asl
@@ -44,7 +44,7 @@ Method(\_PTS, 1) {
 
 	/* On older chips, clear PciExpWakeDisEn */
 	/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-	*    	Store(0,\_SB.PWDE)
+	*	Store(0,\_SB.PWDE)
 	*}
 	*/
 
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index f840382bdc..e69564ea8e 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -170,8 +170,8 @@
 #if IS_ENABLED(CONFIG_GFXUMA)
 #define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
 #define BLDCFG_UMA_ALLOCATION_MODE		  UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE      	  0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
-#define BLDCFG_UMA_ALLOCATION_SIZE      	  0x2000//512M
+//#define BLDCFG_UMA_ALLOCATION_SIZE	  	  0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
+#define BLDCFG_UMA_ALLOCATION_SIZE	  	  0x2000//512M
 #define BLDCFG_UMA_ABOVE4G_SUPPORT                FALSE
 #endif
 
diff --git a/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl b/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl
index c2757fa248..ee49daeaab 100644
--- a/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl
+++ b/src/mainboard/asus/kcma-d8/acpi/pm_ctrl.asl
@@ -129,9 +129,9 @@ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
 	PWMK, 1,
 	PWNS, 1,
 
-	/* 	Offset(0x61), */	/*  Options_1 */
-	/* 		,7,  */
-	/* 		R617,1, */
+	/*	Offset(0x61), */	/*  Options_1 */
+	/*		,7,  */
+	/*		R617,1, */
 
 	Offset(0x65),	/* UsbPMControl */
 	, 4,
diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl
index f1bc896a79..5754d7c2bc 100644
--- a/src/mainboard/asus/kcma-d8/dsdt.asl
+++ b/src/mainboard/asus/kcma-d8/dsdt.asl
@@ -113,7 +113,7 @@ DefinitionBlock (
 			Notify (\_SB.PCI0.PCE4, 0x02)		/* NOTIFY_DEVICE_WAKE */
 		}
 
-	} 	/* End Scope GPE */
+	}	/* End Scope GPE */
 
 	/* Root of the bus hierarchy */
 	Scope (\_SB)
diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c
index 937f4b7552..0de14adbbe 100644
--- a/src/mainboard/asus/kcma-d8/resourcemap.c
+++ b/src/mainboard/asus/kcma-d8/resourcemap.c
@@ -226,7 +226,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-// 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -481,7 +481,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-// 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index 9b121d1c69..a14f7e38d0 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -546,7 +546,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
 	        dump_spd_registers(&cpu[0]);
-        	dump_smbus_registers();
+		dump_smbus_registers();
 	}
 #endif
 
diff --git a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl
index c2757fa248..ee49daeaab 100644
--- a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl
+++ b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl
@@ -129,9 +129,9 @@ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
 	PWMK, 1,
 	PWNS, 1,
 
-	/* 	Offset(0x61), */	/*  Options_1 */
-	/* 		,7,  */
-	/* 		R617,1, */
+	/*	Offset(0x61), */	/*  Options_1 */
+	/*		,7,  */
+	/*		R617,1, */
 
 	Offset(0x65),	/* UsbPMControl */
 	, 4,
diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl
index 6a25b4dd75..ab6547ceb5 100644
--- a/src/mainboard/asus/kgpe-d16/dsdt.asl
+++ b/src/mainboard/asus/kgpe-d16/dsdt.asl
@@ -115,7 +115,7 @@ DefinitionBlock (
 			Notify (\_SB.PCI0.PCE3, 0x02)		/* NOTIFY_DEVICE_WAKE */
 		}
 
-	} 	/* End Scope GPE */
+	}	/* End Scope GPE */
 
 	/* Root of the bus hierarchy */
 	Scope (\_SB)
diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c
index d1fcad7d5a..dcd7f774a7 100644
--- a/src/mainboard/asus/kgpe-d16/resourcemap.c
+++ b/src/mainboard/asus/kgpe-d16/resourcemap.c
@@ -226,7 +226,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-// 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -481,7 +481,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-// 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 89b654f149..9f3e7310fb 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -587,7 +587,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
 	        dump_spd_registers(&cpu[0]);
-        	dump_smbus_registers();
+		dump_smbus_registers();
 	}
 #endif
 
diff --git a/src/mainboard/asus/m4a78-em/devicetree.cb b/src/mainboard/asus/m4a78-em/devicetree.cb
index e760c17e39..f336c2bd82 100644
--- a/src/mainboard/asus/m4a78-em/devicetree.cb
+++ b/src/mainboard/asus/m4a78-em/devicetree.cb
@@ -9,7 +9,7 @@ chip northbridge/amd/amdfam10/root_complex
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
-					device pci 0.0 on end # HT  	0x9600
+					device pci 0.0 on end # HT	0x9600
 					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
 					device pci 3.0 on end # PCIE P2P bridge	0x960b
@@ -40,7 +40,7 @@ chip northbridge/amd/amdfam10/root_complex
 					device pci 13.0 on end # USB
 					device pci 13.1 on end # USB
 					device pci 13.2 on end # USB
-	 				device pci 14.0 on # SM
+					device pci 14.0 on # SM
 						chip drivers/generic/generic #dimm 0-0-0
 							device i2c 50 on end
 						end
diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl
index 905d671bea..e9664d2b99 100644
--- a/src/mainboard/asus/m4a78-em/dsdt.asl
+++ b/src/mainboard/asus/m4a78-em/dsdt.asl
@@ -239,9 +239,9 @@ DefinitionBlock (
 		PWMK, 1,
 		PWNS, 1,
 
-		/* 	Offset(0x61), */	/*  Options_1 */
-		/* 		,7,  */
-		/* 		R617,1, */
+		/*	Offset(0x61), */	/*  Options_1 */
+		/*		,7,  */
+		/*		R617,1, */
 
 		Offset(0x65),	/* UsbPMControl */
 		, 4,
@@ -837,7 +837,7 @@ DefinitionBlock (
 
 		/* On older chips, clear PciExpWakeDisEn */
 		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*    	Store(0,\_SB.PWDE)
+		*	Store(0,\_SB.PWDE)
 		*}
 		*/
 
@@ -853,13 +853,13 @@ DefinitionBlock (
 	*  used, so it could be removed.
 	*
 	*
-	*  	\_GTS OEM Going To Sleep method
+	*	\_GTS OEM Going To Sleep method
 	*
-	*  	Entry:
-	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
 	*
-	*  	Exit:
-	*  		-none-
+	*	Exit:
+	*		-none-
 	*
 	*  Method(\_GTS, 1) {
 	*  DBGO("\\_GTS\n")
@@ -1026,7 +1026,7 @@ DefinitionBlock (
 
 		/*  PCIe HotPlug event  */
 		/* Method(_L0F) {
-		* 	DBGO("\\_GPE\\_L0F\n")
+		*	DBGO("\\_GPE\\_L0F\n")
 		* }
 		*/
 
@@ -1049,19 +1049,19 @@ DefinitionBlock (
 
 		/*  GPM0 SCI event - Moved to USB.asl */
 		/* Method(_L13) {
-		* 	DBGO("\\_GPE\\_L13\n")
+		*	DBGO("\\_GPE\\_L13\n")
 		* }
 		*/
 
 		/*  GPM1 SCI event - Moved to USB.asl */
 		/* Method(_L14) {
-		* 	DBGO("\\_GPE\\_L14\n")
+		*	DBGO("\\_GPE\\_L14\n")
 		* }
 		*/
 
 		/*  GPM2 SCI event - Moved to USB.asl */
 		/* Method(_L15) {
-		* 	DBGO("\\_GPE\\_L15\n")
+		*	DBGO("\\_GPE\\_L15\n")
 		* }
 		*/
 
@@ -1073,7 +1073,7 @@ DefinitionBlock (
 
 		/*  GPM8 SCI event - Moved to USB.asl */
 		/* Method(_L17) {
-		* 	DBGO("\\_GPE\\_L17\n")
+		*	DBGO("\\_GPE\\_L17\n")
 		* }
 		*/
 
@@ -1090,7 +1090,7 @@ DefinitionBlock (
 
 		/*  GPM4 SCI event - Moved to USB.asl */
 		/* Method(_L19) {
-		* 	DBGO("\\_GPE\\_L19\n")
+		*	DBGO("\\_GPE\\_L19\n")
 		* }
 		*/
 
@@ -1121,7 +1121,7 @@ DefinitionBlock (
 
 		/*  GPIO2 or GPIO66 SCI event  */
 		/* Method(_L1E) {
-		* 	DBGO("\\_GPE\\_L1E\n")
+		*	DBGO("\\_GPE\\_L1E\n")
 		* }
 		*/
 
@@ -1131,7 +1131,7 @@ DefinitionBlock (
 		* }
 		*/
 
-	} 	/* End Scope GPE */
+	}	/* End Scope GPE */
 
 	#include "acpi/usb.asl"
 
@@ -1520,7 +1520,7 @@ DefinitionBlock (
 				)
 
 				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)	/* VGA memory space */
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 
@@ -1634,7 +1634,7 @@ DefinitionBlock (
 
 				/* On older chips, clear PciExpWakeDisEn */
 				/*if (LLessEqual(\SBRI, 0x13)) {
-				*    	Store(0,\PWDE)
+				*	Store(0,\PWDE)
 				* }
 				*/
 			} /* End Method(_SB._INI) */
diff --git a/src/mainboard/asus/m4a785-m/devicetree.cb b/src/mainboard/asus/m4a785-m/devicetree.cb
index 4549ead77e..9dc937ccc7 100644
--- a/src/mainboard/asus/m4a785-m/devicetree.cb
+++ b/src/mainboard/asus/m4a785-m/devicetree.cb
@@ -9,7 +9,7 @@ chip northbridge/amd/amdfam10/root_complex
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
-					device pci 0.0 on end # HT  	0x9600
+					device pci 0.0 on end # HT	0x9600
 					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
 					device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
 					device pci 3.0 off end # PCIE P2P bridge	0x960b
@@ -40,7 +40,7 @@ chip northbridge/amd/amdfam10/root_complex
 					device pci 13.0 on end # USB
 					device pci 13.1 on end # USB
 					device pci 13.2 on end # USB
-	 				device pci 14.0 on # SM
+					device pci 14.0 on # SM
 						chip drivers/generic/generic #dimm 0-0-0
 							device i2c 50 on end
 						end
diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl
index 905d671bea..e9664d2b99 100644
--- a/src/mainboard/asus/m4a785-m/dsdt.asl
+++ b/src/mainboard/asus/m4a785-m/dsdt.asl
@@ -239,9 +239,9 @@ DefinitionBlock (
 		PWMK, 1,
 		PWNS, 1,
 
-		/* 	Offset(0x61), */	/*  Options_1 */
-		/* 		,7,  */
-		/* 		R617,1, */
+		/*	Offset(0x61), */	/*  Options_1 */
+		/*		,7,  */
+		/*		R617,1, */
 
 		Offset(0x65),	/* UsbPMControl */
 		, 4,
@@ -837,7 +837,7 @@ DefinitionBlock (
 
 		/* On older chips, clear PciExpWakeDisEn */
 		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*    	Store(0,\_SB.PWDE)
+		*	Store(0,\_SB.PWDE)
 		*}
 		*/
 
@@ -853,13 +853,13 @@ DefinitionBlock (
 	*  used, so it could be removed.
 	*
 	*
-	*  	\_GTS OEM Going To Sleep method
+	*	\_GTS OEM Going To Sleep method
 	*
-	*  	Entry:
-	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
 	*
-	*  	Exit:
-	*  		-none-
+	*	Exit:
+	*		-none-
 	*
 	*  Method(\_GTS, 1) {
 	*  DBGO("\\_GTS\n")
@@ -1026,7 +1026,7 @@ DefinitionBlock (
 
 		/*  PCIe HotPlug event  */
 		/* Method(_L0F) {
-		* 	DBGO("\\_GPE\\_L0F\n")
+		*	DBGO("\\_GPE\\_L0F\n")
 		* }
 		*/
 
@@ -1049,19 +1049,19 @@ DefinitionBlock (
 
 		/*  GPM0 SCI event - Moved to USB.asl */
 		/* Method(_L13) {
-		* 	DBGO("\\_GPE\\_L13\n")
+		*	DBGO("\\_GPE\\_L13\n")
 		* }
 		*/
 
 		/*  GPM1 SCI event - Moved to USB.asl */
 		/* Method(_L14) {
-		* 	DBGO("\\_GPE\\_L14\n")
+		*	DBGO("\\_GPE\\_L14\n")
 		* }
 		*/
 
 		/*  GPM2 SCI event - Moved to USB.asl */
 		/* Method(_L15) {
-		* 	DBGO("\\_GPE\\_L15\n")
+		*	DBGO("\\_GPE\\_L15\n")
 		* }
 		*/
 
@@ -1073,7 +1073,7 @@ DefinitionBlock (
 
 		/*  GPM8 SCI event - Moved to USB.asl */
 		/* Method(_L17) {
-		* 	DBGO("\\_GPE\\_L17\n")
+		*	DBGO("\\_GPE\\_L17\n")
 		* }
 		*/
 
@@ -1090,7 +1090,7 @@ DefinitionBlock (
 
 		/*  GPM4 SCI event - Moved to USB.asl */
 		/* Method(_L19) {
-		* 	DBGO("\\_GPE\\_L19\n")
+		*	DBGO("\\_GPE\\_L19\n")
 		* }
 		*/
 
@@ -1121,7 +1121,7 @@ DefinitionBlock (
 
 		/*  GPIO2 or GPIO66 SCI event  */
 		/* Method(_L1E) {
-		* 	DBGO("\\_GPE\\_L1E\n")
+		*	DBGO("\\_GPE\\_L1E\n")
 		* }
 		*/
 
@@ -1131,7 +1131,7 @@ DefinitionBlock (
 		* }
 		*/
 
-	} 	/* End Scope GPE */
+	}	/* End Scope GPE */
 
 	#include "acpi/usb.asl"
 
@@ -1520,7 +1520,7 @@ DefinitionBlock (
 				)
 
 				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)	/* VGA memory space */
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 
@@ -1634,7 +1634,7 @@ DefinitionBlock (
 
 				/* On older chips, clear PciExpWakeDisEn */
 				/*if (LLessEqual(\SBRI, 0x13)) {
-				*    	Store(0,\PWDE)
+				*	Store(0,\PWDE)
 				* }
 				*/
 			} /* End Method(_SB._INI) */
diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb
index 9783989424..6fce0f377c 100644
--- a/src/mainboard/asus/m4a785t-m/devicetree.cb
+++ b/src/mainboard/asus/m4a785t-m/devicetree.cb
@@ -9,7 +9,7 @@ chip northbridge/amd/amdfam10/root_complex
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
-					device pci 0.0 on end # HT  	0x9600
+					device pci 0.0 on end # HT	0x9600
 					device pci 1.0 on # Internal Graphics P2P bridge 0x9602
 						device pci 5.0 on end # onboard VGA
 					end
@@ -42,7 +42,7 @@ chip northbridge/amd/amdfam10/root_complex
 					device pci 13.0 on end # USB
 					device pci 13.1 on end # USB
 					device pci 13.2 on end # USB
-	 				device pci 14.0 on # SM
+					device pci 14.0 on # SM
 						chip drivers/generic/generic #dimm 0-0-0
 							device i2c 50 on end
 						end
diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl
index 3220cae582..32b781788a 100644
--- a/src/mainboard/asus/m4a785t-m/dsdt.asl
+++ b/src/mainboard/asus/m4a785t-m/dsdt.asl
@@ -239,9 +239,9 @@ DefinitionBlock (
 		PWMK, 1,
 		PWNS, 1,
 
-		/* 	Offset(0x61), */	/*  Options_1 */
-		/* 		,7,  */
-		/* 		R617,1, */
+		/*	Offset(0x61), */	/*  Options_1 */
+		/*		,7,  */
+		/*		R617,1, */
 
 		Offset(0x65),	/* UsbPMControl */
 		, 4,
@@ -837,7 +837,7 @@ DefinitionBlock (
 
 		/* On older chips, clear PciExpWakeDisEn */
 		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*    	Store(0,\_SB.PWDE)
+		*	Store(0,\_SB.PWDE)
 		*}
 		*/
 
@@ -853,13 +853,13 @@ DefinitionBlock (
 	*  used, so it could be removed.
 	*
 	*
-	*  	\_GTS OEM Going To Sleep method
+	*	\_GTS OEM Going To Sleep method
 	*
-	*  	Entry:
-	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
 	*
-	*  	Exit:
-	*  		-none-
+	*	Exit:
+	*		-none-
 	*
 	*  Method(\_GTS, 1) {
 	*  DBGO("\\_GTS\n")
@@ -1026,7 +1026,7 @@ DefinitionBlock (
 
 		/*  PCIe HotPlug event  */
 		/* Method(_L0F) {
-		* 	DBGO("\\_GPE\\_L0F\n")
+		*	DBGO("\\_GPE\\_L0F\n")
 		* }
 		*/
 
@@ -1049,19 +1049,19 @@ DefinitionBlock (
 
 		/*  GPM0 SCI event - Moved to USB.asl */
 		/* Method(_L13) {
-		* 	DBGO("\\_GPE\\_L13\n")
+		*	DBGO("\\_GPE\\_L13\n")
 		* }
 		*/
 
 		/*  GPM1 SCI event - Moved to USB.asl */
 		/* Method(_L14) {
-		* 	DBGO("\\_GPE\\_L14\n")
+		*	DBGO("\\_GPE\\_L14\n")
 		* }
 		*/
 
 		/*  GPM2 SCI event - Moved to USB.asl */
 		/* Method(_L15) {
-		* 	DBGO("\\_GPE\\_L15\n")
+		*	DBGO("\\_GPE\\_L15\n")
 		* }
 		*/
 
@@ -1073,7 +1073,7 @@ DefinitionBlock (
 
 		/*  GPM8 SCI event - Moved to USB.asl */
 		/* Method(_L17) {
-		* 	DBGO("\\_GPE\\_L17\n")
+		*	DBGO("\\_GPE\\_L17\n")
 		* }
 		*/
 
@@ -1090,7 +1090,7 @@ DefinitionBlock (
 
 		/*  GPM4 SCI event - Moved to USB.asl */
 		/* Method(_L19) {
-		* 	DBGO("\\_GPE\\_L19\n")
+		*	DBGO("\\_GPE\\_L19\n")
 		* }
 		*/
 
@@ -1121,7 +1121,7 @@ DefinitionBlock (
 
 		/*  GPIO2 or GPIO66 SCI event  */
 		/* Method(_L1E) {
-		* 	DBGO("\\_GPE\\_L1E\n")
+		*	DBGO("\\_GPE\\_L1E\n")
 		* }
 		*/
 
@@ -1131,7 +1131,7 @@ DefinitionBlock (
 		* }
 		*/
 
-	} 	/* End Scope GPE */
+	}	/* End Scope GPE */
 
 	#include "acpi/usb.asl"
 
@@ -1505,7 +1505,7 @@ DefinitionBlock (
 				)
 
 				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)	/* VGA memory space */
 				/* memory space for PCI BARs below 4GB */
 				Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
 			}) /* End Name(_SB.PCI0.CRES) */
@@ -1557,7 +1557,7 @@ DefinitionBlock (
 
 				/* On older chips, clear PciExpWakeDisEn */
 				/*if (LLessEqual(\SBRI, 0x13)) {
-				*    	Store(0,\PWDE)
+				*	Store(0,\PWDE)
 				* }
 				*/
 			} /* End Method(_SB._INI) */
diff --git a/src/mainboard/asus/m5a88-v/devicetree.cb b/src/mainboard/asus/m5a88-v/devicetree.cb
index 65ddf30e30..d0efbdf6e5 100644
--- a/src/mainboard/asus/m5a88-v/devicetree.cb
+++ b/src/mainboard/asus/m5a88-v/devicetree.cb
@@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex
 		chip northbridge/amd/amdfam10
 			device pci 18.0 on #  northbridge
 				chip southbridge/amd/rs780
-					device pci 0.0 on end # HT  	0x9600
+					device pci 0.0 on end # HT	0x9600
 					device pci 1.0 on end # Internal Graphics P2P bridge 0x9712
 					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
 					device pci 3.0 off end # PCIE P2P bridge 0x960b
diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl
index be1dead802..ff794a0e97 100644
--- a/src/mainboard/asus/m5a88-v/dsdt.asl
+++ b/src/mainboard/asus/m5a88-v/dsdt.asl
@@ -234,9 +234,9 @@ DefinitionBlock (
 		PWMK, 1,
 		PWNS, 1,
 
-		/* 	Offset(0x61), */	/*  Options_1 */
-		/* 		,7,  */
-		/* 		R617,1, */
+		/*	Offset(0x61), */	/*  Options_1 */
+		/*		,7,  */
+		/*		R617,1, */
 
 		Offset(0x65),	/* UsbPMControl */
 		, 4,
@@ -832,7 +832,7 @@ DefinitionBlock (
 
 		/* On older chips, clear PciExpWakeDisEn */
 		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*    	Store(0,\_SB.PWDE)
+		*	Store(0,\_SB.PWDE)
 		*}
 		*/
 
@@ -847,13 +847,13 @@ DefinitionBlock (
 	*  used, so it could be removed.
 	*
 	*
-	*  	\_GTS OEM Going To Sleep method
+	*	\_GTS OEM Going To Sleep method
 	*
-	*  	Entry:
-	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
 	*
-	*  	Exit:
-	*  		-none-
+	*	Exit:
+	*		-none-
 	*
 	*  Method(\_GTS, 1) {
 	*  DBGO("\\_GTS\n")
@@ -1020,7 +1020,7 @@ DefinitionBlock (
 
 		/*  PCIe HotPlug event  */
 		/* Method(_L0F) {
-		* 	DBGO("\\_GPE\\_L0F\n")
+		*	DBGO("\\_GPE\\_L0F\n")
 		* }
 		*/
 
@@ -1043,19 +1043,19 @@ DefinitionBlock (
 
 		/*  GPM0 SCI event - Moved to USB.asl */
 		/* Method(_L13) {
-		* 	DBGO("\\_GPE\\_L13\n")
+		*	DBGO("\\_GPE\\_L13\n")
 		* }
 		*/
 
 		/*  GPM1 SCI event - Moved to USB.asl */
 		/* Method(_L14) {
-		* 	DBGO("\\_GPE\\_L14\n")
+		*	DBGO("\\_GPE\\_L14\n")
 		* }
 		*/
 
 		/*  GPM2 SCI event - Moved to USB.asl */
 		/* Method(_L15) {
-		* 	DBGO("\\_GPE\\_L15\n")
+		*	DBGO("\\_GPE\\_L15\n")
 		* }
 		*/
 
@@ -1067,7 +1067,7 @@ DefinitionBlock (
 
 		/*  GPM8 SCI event - Moved to USB.asl */
 		/* Method(_L17) {
-		* 	DBGO("\\_GPE\\_L17\n")
+		*	DBGO("\\_GPE\\_L17\n")
 		* }
 		*/
 
@@ -1084,7 +1084,7 @@ DefinitionBlock (
 
 		/*  GPM4 SCI event - Moved to USB.asl */
 		/* Method(_L19) {
-		* 	DBGO("\\_GPE\\_L19\n")
+		*	DBGO("\\_GPE\\_L19\n")
 		* }
 		*/
 
@@ -1115,7 +1115,7 @@ DefinitionBlock (
 
 		/*  GPIO2 or GPIO66 SCI event  */
 		/* Method(_L1E) {
-		* 	DBGO("\\_GPE\\_L1E\n")
+		*	DBGO("\\_GPE\\_L1E\n")
 		* }
 		*/
 
@@ -1125,7 +1125,7 @@ DefinitionBlock (
 		* }
 		*/
 
-	} 	/* End Scope GPE */
+	}	/* End Scope GPE */
 
 	#include "acpi/usb.asl"
 
@@ -1477,7 +1477,7 @@ DefinitionBlock (
 				)
 #if 0
 				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)	/* VGA memory space */
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 
@@ -1607,7 +1607,7 @@ DefinitionBlock (
 
 				/* On older chips, clear PciExpWakeDisEn */
 				/*if (LLessEqual(\SBRI, 0x13)) {
-				*    	Store(0,\PWDE)
+				*	Store(0,\PWDE)
 				* }
 				*/
 			} /* End Method(_SB._INI) */