diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-22 08:37:15 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-01 05:47:51 +0100 |
| commit | de43dd631402e326bbfb3fa6fa3bd92cb497871c (patch) | |
| tree | 0d1d464750f206c395fc8a18ee476b696275b1b1 /src | |
| parent | 7d25651ed3eb78228a00b479454d0ab2417f3f2a (diff) | |
| download | coreboot-de43dd631402e326bbfb3fa6fa3bd92cb497871c.tar.xz | |
asus/f2a85-m msi/ms7721: Enable MMCONF early
PCI MMCONF access only works after amd_initmmio() call.
Change-Id: I5765604e178d09abdd6bb6ce7cc220bc5b35ed03
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/asus/f2a85-m/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/msi/ms7721/romstage.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 0e502e717f..83f6778f49 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -64,6 +64,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; + amd_initmmio(); + #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); #endif @@ -71,8 +73,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); #endif - amd_initmmio(); - if (!cpu_init_detectedx && boot_cpu()) { /* enable SIO LPC decode */ diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 599187d4c0..f8565adec6 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -128,6 +128,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; + amd_initmmio(); + #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); #endif @@ -135,8 +137,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); #endif - amd_initmmio(); - if (!cpu_init_detectedx && boot_cpu()) { /* enable SIO LPC decode */ |