diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-11-18 14:08:08 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-26 11:50:52 +0000 |
| commit | e1470ea6a3b83473b5fca54b93d3c12834660980 (patch) | |
| tree | 54e1a8d3be73ec183088f6a870c7ea725d0d946d /src | |
| parent | 433acc2d3d6cfb3d16030cbba7be9a5defccf057 (diff) | |
| download | coreboot-e1470ea6a3b83473b5fca54b93d3c12834660980.tar.xz | |
soc/intel/cannonlake: Add chip config to override CPU flex ratio
This patch provides options to override descriptor default CPU flex
ratio from coreboot code. cpu_ratio_override to provide the required CPU
ratio.
Note: Don't override the flex ratio if cpu_ratio is 0.
BUG=b:142264107
TEST=Without override flex_ratio is 0 and verified booting to
OS after overriding with flex_ratio value 5.
Change-Id: Ib01650f52f3d402f669e7e7f5b28a648b86f08ec
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 13 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 12 |
2 files changed, 21 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 17afdd10da..507290f504 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -424,6 +424,19 @@ struct soc_intel_cannonlake_config { * Bit 0: MISCCFG_GPDLCGEN */ uint8_t gpio_pm[TOTAL_GPIO_COMM]; + + /* + * Override CPU flex ratio value: + * CPU ratio value controls the maximum processor non-turbo ratio. + * Valid Range 0 to 63. + * + * In general descriptor provides option to set default cpu flex ratio. + * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. + * Thats the reason FSP skips cpu_ratio override if cpu_ratio is 0. + * + * Only override CPU flex ratio if don't want to boot with non-turbo max. + */ + uint8_t cpu_ratio_override; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 996c13577e..5c74d4a1e0 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -74,10 +74,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; #endif - /* Set CpuRatio to match existing MSR value */ - msr_t flex_ratio; - flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + if (config->cpu_ratio_override) { + m_cfg->CpuRatio = config->cpu_ratio_override; + } else { + /* Set CpuRatio to match existing MSR value */ + msr_t flex_ratio; + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; + } /* If ISH is enabled, enable ISH elements */ if (!dev) |