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| author | Patrick Georgi <pgeorgi@chromium.org> | 2016-07-29 18:53:34 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 19:01:56 +0200 |
| commit | e8f2ef51e1809b8c20d87049586935a7f3dd90a7 (patch) | |
| tree | 9a421629de206570234d23c1e9e7b01530abe009 /src | |
| parent | 90ed31beac54f6380a78a4b3c51c8fab434db95b (diff) | |
| download | coreboot-e8f2ef51e1809b8c20d87049586935a7f3dd90a7.tar.xz | |
intel/broadwell: fix typo
(pci_read_config32(...) > 14) & 0x3 looks rather unusual (and prevents
"case 3" below from ever happening)
Change-Id: Id90655c39ff53da9569441278bbf73497d643480
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1293139
Reviewed-on: https://review.coreboot.org/15965
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/broadwell/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 41d66e2f2a..1c9b50cceb 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -99,7 +99,7 @@ static void root_port_config_update_gbe_port(void) static void pcie_iosf_port_grant_count(device_t dev) { u8 update_val; - u32 rpcd = (pci_read_config32(dev, 0xfc) > 14) & 0x3; + u32 rpcd = (pci_read_config32(dev, 0xfc) >> 14) & 0x3; switch (rpcd) { case 1: |