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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2020-06-17 17:35:25 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-07-06 06:08:24 +0000
commite927d9b3adc9c5a4e4cc6757949f626458a80e68 (patch)
tree6b9fe89e08f6384e18cfb60f42c8878ad2820716 /src
parenta8b80942a08177cb6c318f084e6a9c17668753fc (diff)
downloadcoreboot-e927d9b3adc9c5a4e4cc6757949f626458a80e68.tar.xz
soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
Since coreboot is initializing uart for debug logs, fsp should not reinitialize it. Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot BUG=None BRANCH=None TEST=FSP is able to push debug logs on UART with this setting Cq-Depend: TBD Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/jasperlake/romstage/fsp_params.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index d9063b0b0c..6d4055ab51 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -81,6 +81,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->VtdDisable = 0;
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+ m_cfg->SerialIoUartDebugMode = config->SerialIoUartMode[CONFIG_UART_FOR_CONSOLE];
/* Display */
m_cfg->DdiPortAConfig = config->DdiPortAConfig;