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| author | Zheng Bao <zheng.bao@amd.com> | 2009-08-11 03:18:11 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2009-08-11 03:18:11 +0000 |
| commit | edee9eb350406e8c1598bb455815469c13c089b9 (patch) | |
| tree | 376dfc0bbe44427392f46c70742abfb1b032f777 /src | |
| parent | dabae0d8fc0fce8f56bd43239cf965814c433d38 (diff) | |
| download | coreboot-edee9eb350406e8c1598bb455815469c13c089b9.tar.xz | |
The code between #if and #endif is only about UMA mode. The CONFIG_GFXUMA should be 1.
We have another mode called side port mode. It is When the CONFIG_GFXUMA is 0.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/x86/mtrr/mtrr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 9129a1aa53..7b8d43c1f1 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -418,7 +418,7 @@ void x86_setup_var_mtrrs(unsigned address_bits) search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_var_mtrr_resource, &var_state); -#ifdef CONFIG_GFXUMA +#if (CONFIG_GFXUMA == 1) /* UMA or SP. */ // For now we assume the UMA space is at the end of memory if (var_state.hole_startk || var_state.hole_sizek) { printk_debug("Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n"); |