Intel i82830 boards & chips: Remove - using LATE_CBMEM_INIT

All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.

If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.

chips:
cpu/intel/socket_mFCBGA479
northbridge/intel/i82830

Mainboards:
mainboard/rca/rm4100
mainboard/thomson/ip1000

Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

37 files changed, 0 insertions, 2380 deletions

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index cc227b3bf0..0f3eaf46b5 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -43,10 +43,6 @@ cbfs-files-$(CONFIG_VGA_BIOS) += pci$(stripped_vgabios_id).rom
 pci$(stripped_vgabios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_FILE))
 pci$(stripped_vgabios_id).rom-type := optionrom
 
-cbfs-files-$(CONFIG_INTEL_MBI) += mbi.bin
-mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE))
-mbi.bin-type := mbi
-
 ###############################################################################
 # common support for early assembly includes
 ###############################################################################
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 4871db3388..fdd341a7bb 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -10,7 +10,6 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA1023) += socket_FCBGA1023
-subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN
diff --git a/src/cpu/intel/socket_mFCBGA479/Kconfig b/src/cpu/intel/socket_mFCBGA479/Kconfig
deleted file mode 100644
index 74508549e3..0000000000
--- a/src/cpu/intel/socket_mFCBGA479/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-config CPU_INTEL_SOCKET_MFCBGA479
-	bool
-	select CPU_INTEL_MODEL_6BX
-	select MMX
-	select SSE
-
-if CPU_INTEL_SOCKET_MFCBGA479
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xc8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x08000
-
-endif
diff --git a/src/cpu/intel/socket_mFCBGA479/Makefile.inc b/src/cpu/intel/socket_mFCBGA479/Makefile.inc
deleted file mode 100644
index 918a54e800..0000000000
--- a/src/cpu/intel/socket_mFCBGA479/Makefile.inc
+++ /dev/null
@@ -1,10 +0,0 @@
-subdirs-y += ../model_6bx
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
-subdirs-y += ../microcode
-
-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage_legacy.c
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 28298d55d3..99eedab108 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -605,23 +605,6 @@ config INTEL_GMA_VBT_FILE
 	help
 	  The path and filename of the VBT binary.
 
-config INTEL_MBI
-	bool "Add an MBI image"
-	depends on NORTHBRIDGE_INTEL_I82830
-	help
-	  Select this option if you have an Intel MBI image that you would
-	  like to add to your ROM.
-
-	  You will be able to specify the location and file name of the
-	  image later.
-
-config MBI_FILE
-	string "Intel MBI path and filename"
-	depends on INTEL_MBI
-	default "mbi.bin"
-	help
-	  The path and filename of the file to use as VGA BIOS.
-
 config SOFTWARE_I2C
 	bool "Enable I2C controller emulation in software"
 	default n
diff --git a/src/mainboard/rca/Kconfig b/src/mainboard/rca/Kconfig
deleted file mode 100644
index d5728f2e67..0000000000
--- a/src/mainboard/rca/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_RCA
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/rca/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/rca/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	string
-	default "RCA"
-
-endif # VENDOR_RCA
diff --git a/src/mainboard/rca/Kconfig.name b/src/mainboard/rca/Kconfig.name
deleted file mode 100644
index 353499679a..0000000000
--- a/src/mainboard/rca/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_RCA
-	bool "RCA"
diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig
deleted file mode 100644
index 81cfc7b999..0000000000
--- a/src/mainboard/rca/rm4100/Kconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-if BOARD_RCA_RM4100
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_INTEL_SOCKET_MFCBGA479
-	select NORTHBRIDGE_INTEL_I82830
-	select SOUTHBRIDGE_INTEL_I82801DX
-	select SUPERIO_SMSC_SMSCSUPERIO
-	select HAVE_PIRQ_TABLE
-	select BOARD_ROMSIZE_KB_1024
-
-config MAINBOARD_DIR
-	string
-	default rca/rm4100
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "RM4100"
-
-config IRQ_SLOT_COUNT
-	int
-	default 7
-
-endif # BOARD_RCA_RM4100
diff --git a/src/mainboard/rca/rm4100/Kconfig.name b/src/mainboard/rca/rm4100/Kconfig.name
deleted file mode 100644
index fd737abbd1..0000000000
--- a/src/mainboard/rca/rm4100/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_RCA_RM4100
-	bool "RM4100"
diff --git a/src/mainboard/rca/rm4100/board_info.txt b/src/mainboard/rca/rm4100/board_info.txt
deleted file mode 100644
index 0c06a7d7eb..0000000000
--- a/src/mainboard/rca/rm4100/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: settop
-Board URL: http://www.settoplinux.org/index.php?title=RCA_RM4100
-Flashrom support: y
diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb
deleted file mode 100644
index 7c31423c6d..0000000000
--- a/src/mainboard/rca/rm4100/devicetree.cb
+++ /dev/null
@@ -1,67 +0,0 @@
-chip northbridge/intel/i82830		# Northbridge
-  device cpu_cluster 0 on		# APIC cluster
-    chip cpu/intel/socket_mFCBGA479	# Mobile Celeron Micro-FCBGA Socket 479
-      device lapic 0 on end		# APIC
-    end
-  end
-  device domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    chip southbridge/intel/i82801dx	# Southbridge
-      register "pirqa_routing" = "0x05"
-      register "pirqb_routing" = "0x06"
-      register "pirqc_routing" = "0x07"
-      register "pirqd_routing" = "0x09"
-      register "pirqe_routing" = "0x0a"
-      register "pirqf_routing" = "0x80"
-      register "pirqg_routing" = "0x80"
-      register "pirqh_routing" = "0x0b"
-
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1d.0 on end		# USB UHCI Controller #1
-      device pci 1d.1 on end		# USB UHCI Controller #2
-      device pci 1d.2 on end		# USB UHCI Controller #3
-      device pci 1d.7 on end		# USB2 EHCI Controller
-      device pci 1e.0 on end		# PCI bridge
-      device pci 1f.0 on		# ISA/LPC bridge
-        chip superio/smsc/smscsuperio	# Super I/O
-          device pnp 2e.0 off		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 4
-          end
-          device pnp 2e.4 on		# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.5 on		# Com2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.7 on		# PS/2 keyboard/mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# Keyboard interrupt
-            irq 0x72 = 12		# Mouse interrupt
-          end
-          device pnp 2e.9 off end	# Game port
-          device pnp 2e.a on		# PME
-            io 0x60 = 0x800
-          end
-          device pnp 2e.b off end	# MPU-401
-        end
-      end
-      device pci 1f.1 on end		# IDE
-      device pci 1f.3 on end		# SMBus
-      device pci 1f.5 on end		# AC'97 audio
-      device pci 1f.6 on end		# AC'97 modem
-    end
-  end
-end
diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c
deleted file mode 100644
index 168bb09def..0000000000
--- a/src/mainboard/rca/rm4100/gpio.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-
-#define PME_DEV			PNP_DEV(0x2e, 0x0a)
-#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
-#define ICH_IO_BASE_ADDR	0x00000500 /* GPIO base address register */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-	pci_devfn_t dev;
-	uint16_t port;
-	uint32_t set_gpio;
-
-	/* Southbridge GPIOs. */
-	/* Set the LPC device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-	/* Set the value for GPIO base address register and enable GPIO. */
-	pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));
-	pci_write_config8(dev, GPIO_CNTL, 0x10);
-
-	/* Set GPIO23 to high, this enables the LAN controller. */
-	udelay(10);
-	set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
-	set_gpio |= 1 << 23;
-	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
-
-	/* Super I/O GPIOs. */
-	dev = PME_DEV;
-	port = dev >> 8;
-
-	/* Enter the configuration state. */
-	outb(0x55, port);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
-	pnp_set_enable(dev, 1);
-
-	/* GP21 - LED_RED */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2c);
-
-	/* GP30 - FAN2_TACH */
-	outl(0x05, PME_IO_BASE_ADDR + 0x33);
-
-	/* GP31 - FAN1_TACH */
-	outl(0x05, PME_IO_BASE_ADDR + 0x34);
-
-	/* GP32 - FAN2_CTRL */
-	outl(0x04, PME_IO_BASE_ADDR + 0x35);
-
-	/* GP33 - FAN1_CTRL */
-	outl(0x04, PME_IO_BASE_ADDR + 0x36);
-
-	/* GP34 - AUD_MUTE_OUT_R */
-	outl(0x00, PME_IO_BASE_ADDR + 0x37);
-
-	/* GP36 - KBRST */
-	outl(0x00, PME_IO_BASE_ADDR + 0x39);
-
-	/* GP37 - A20GATE */
-	outl(0x00, PME_IO_BASE_ADDR + 0x3a);
-
-	/* GP42 - GPIO_PME_OUT */
-	outl(0x00, PME_IO_BASE_ADDR + 0x3d);
-
-	/* GP50 - SER2_RI */
-	outl(0x05, PME_IO_BASE_ADDR + 0x3f);
-
-	/* GP51 - SER2_DCD */
-	outl(0x05, PME_IO_BASE_ADDR + 0x40);
-
-	/* GP52 - SER2_RX */
-	outl(0x05, PME_IO_BASE_ADDR + 0x41);
-
-	/* GP53 - SER2_TX */
-	outl(0x04, PME_IO_BASE_ADDR + 0x42);
-
-	/* GP55 - SER2_RTS */
-	outl(0x04, PME_IO_BASE_ADDR + 0x44);
-
-	/* GP56 - SER2_CTS */
-	outl(0x05, PME_IO_BASE_ADDR + 0x45);
-
-	/* GP57 - SER2_DTR */
-	outl(0x04, PME_IO_BASE_ADDR + 0x46);
-
-	/* GP60 - LED_GREEN */
-	outl(0x01, PME_IO_BASE_ADDR + 0x47);
-
-	/* GP61 - LED_YELLOW */
-	outl(0x01, PME_IO_BASE_ADDR + 0x48);
-
-	/* GP3 */
-	outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
-
-	/* GP4 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x4e);
-
-	/* FAN1 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x56);
-
-	/* FAN2 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x57);
-
-	/* Fan Control */
-	outl(0x50, PME_IO_BASE_ADDR + 0x58);
-
-	/* Fan1 Tachometer */
-	outl(0xff, PME_IO_BASE_ADDR + 0x59);
-
-	/* Fan2 Tachometer */
-	outl(0xff, PME_IO_BASE_ADDR + 0x5a);
-
-	/* LED1 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5d);
-
-	/* LED2 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5e);
-
-	/* Keyboard Scan Code */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5f);
-
-	/* Exit the configuration state. */
-	outb(0xaa, port);
-}
diff --git a/src/mainboard/rca/rm4100/irq_tables.c b/src/mainboard/rca/rm4100/irq_tables.c
deleted file mode 100644
index e99adfcbc5..0000000000
--- a/src/mainboard/rca/rm4100/irq_tables.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,    /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
-	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
-	0,		 /* IRQs devoted exclusively to PCI usage */
-	0x8086,		 /* Vendor */
-	0x24c0,		 /* Device */
-	0,		 /* Miniport data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x07,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x02 << 3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */
-		{0x00,(0x1d << 3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */
-		{0x00,(0x1f << 3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */
-		{0x01,(0x08 << 3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */
-		{0x01,(0x00 << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */
-		{0x01,(0x01 << 3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */
-		{0x01,(0x02 << 3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
deleted file mode 100644
index 43c518f428..0000000000
--- a/src/mainboard/rca/rm4100/romstage.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <lib.h>
-#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include <northbridge/intel/i82830/raminit.h>
-#include "northbridge/intel/i82830/memory_initialized.c"
-#include <southbridge/intel/i82801dx/i82801dx.h>
-#include "southbridge/intel/i82801dx/reset.c"
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include "spd_table.h"
-#include "gpio.c"
-#include "southbridge/intel/i82801dx/tco_timer.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
-/**
- * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
- * values have to be set manually, the SO-DIMM socket is located in
- * socket0 (0x50/DIMM0), and the onboard memory is located in socket1
- * (0x51/DIMM1).
- */
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	int i;
-
-	if (device == DIMM0) {
-		return smbus_read_byte(device, address);
-	} else if (device == DIMM1) {
-		for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
-			if (spd_table[i].address == address)
-				return spd_table[i].data;
-		}
-		return 0xFF; /* Return 0xFF when address is not found. */
-	} else {
-		return 0xFF; /* Return 0xFF on any failures. */
-	}
-}
-
-#include "northbridge/intel/i82830/raminit.c"
-
-/**
- * Setup mainboard specific registers pre raminit.
- */
-static void mb_early_setup(void)
-{
-	/* - Hub Interface to PCI Bridge Registers - */
-	/* 12-Clock Retry Enable */
-	pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
-	/* Master Latency Timer Count */
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
-	/* I/O Address Base */
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);
-
-	/* - LPC Interface Bridge Registers - */
-	/* Delayed Transaction Enable */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
-	/* Disable the TCO Timer system reboot feature */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
-	/* CPU Frequency Strap */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
-	/* ACPI base address and enable Resource Indicator */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
-	/* Enable the SMBUS */
-	enable_smbus();
-	/* ACPI base address and disable Resource Indicator */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR));
-	/*  ACPI Enable */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
-	if (bist == 0) {
-		if (memory_initialized())
-			hard_reset();
-	}
-
-	/* Set southbridge and superio gpios */
-	mb_gpio_init();
-
-	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	/* Halt if there was a built in self test failure. */
-	report_bist_failure(bist);
-
-	/* disable TCO timers */
-	i82801dx_halt_tco_timer();
-
-	/* Setup mainboard specific registers */
-	mb_early_setup();
-
-	/* Initialize memory */
-	sdram_initialize();
-}
diff --git a/src/mainboard/rca/rm4100/smihandler.c b/src/mainboard/rca/rm4100/smihandler.c
deleted file mode 100644
index a8a7aca9f1..0000000000
--- a/src/mainboard/rca/rm4100/smihandler.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-
-int mainboard_io_trap_handler(int smif)
-{
-	printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");
-	return 1;
-}
diff --git a/src/mainboard/rca/rm4100/spd_table.h b/src/mainboard/rca/rm4100/spd_table.h
deleted file mode 100644
index 14bc85b724..0000000000
--- a/src/mainboard/rca/rm4100/spd_table.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <spd.h>
-
-struct spd_entry {
-	unsigned int address;
-	unsigned int data;
-};
-
-/*
- * The onboard 128MB PC133 memory does not have an SPD EEPROM so the values
- * have to be set manually, the onboard memory is located in socket1 (0x51).
- */
-const struct spd_entry spd_table [] = {
-	{SPD_MEMORY_TYPE,                     0x04}, /* (Fundamental) memory type */
-	{SPD_NUM_COLUMNS,                     0x09}, /* Number of column address bits */
-	{SPD_NUM_DIMM_BANKS,                  0x01}, /* Number of module rows (banks) */
-	{SPD_MODULE_DATA_WIDTH_LSB,           0x40}, /* Module data width (LSB) */
-	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX,       0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
-	{SPD_ACCESS_TIME_FROM_CLOCK,          0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
-	{SPD_DENSITY_OF_EACH_ROW_ON_MODULE,   0x20}, /* Density of each row on module */
-};
diff --git a/src/mainboard/thomson/Kconfig b/src/mainboard/thomson/Kconfig
deleted file mode 100644
index e439ba7bb5..0000000000
--- a/src/mainboard/thomson/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_THOMSON
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/thomson/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/thomson/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	string
-	default "Thomson"
-
-endif # VENDOR_THOMSON
diff --git a/src/mainboard/thomson/Kconfig.name b/src/mainboard/thomson/Kconfig.name
deleted file mode 100644
index b22bbbb509..0000000000
--- a/src/mainboard/thomson/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_THOMSON
-	bool "Thomson"
diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig
deleted file mode 100644
index 1c21ace453..0000000000
--- a/src/mainboard/thomson/ip1000/Kconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-if BOARD_THOMSON_IP1000
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_INTEL_SOCKET_MFCBGA479
-	select NORTHBRIDGE_INTEL_I82830
-	select SOUTHBRIDGE_INTEL_I82801DX
-	select SUPERIO_SMSC_SMSCSUPERIO
-	select HAVE_PIRQ_TABLE
-	select BOARD_ROMSIZE_KB_512
-	select INTEL_INT15
-
-config MAINBOARD_DIR
-	string
-	default thomson/ip1000
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "IP1000"
-
-config IRQ_SLOT_COUNT
-	int
-	default 7
-
-choice
-	prompt "IP1000 Onboard Memory"
-	default ONBOARD_MEMORY_64MB
-
-config ONBOARD_MEMORY_64MB
-	bool "IP1000-64MB"
-config ONBOARD_MEMORY_128MB
-	bool "IP1000T-128MB"
-
-endchoice
-
-endif # BOARD_THOMSON_IP1000
diff --git a/src/mainboard/thomson/ip1000/Kconfig.name b/src/mainboard/thomson/ip1000/Kconfig.name
deleted file mode 100644
index ad3d884883..0000000000
--- a/src/mainboard/thomson/ip1000/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_THOMSON_IP1000
-	bool "IP1000"
diff --git a/src/mainboard/thomson/ip1000/board_info.txt b/src/mainboard/thomson/ip1000/board_info.txt
deleted file mode 100644
index 77f089550e..0000000000
--- a/src/mainboard/thomson/ip1000/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: settop
-Board URL: http://www.settoplinux.org/index.php?title=Thomson_IP1000
-Flashrom support: y
diff --git a/src/mainboard/thomson/ip1000/devicetree.cb b/src/mainboard/thomson/ip1000/devicetree.cb
deleted file mode 100644
index 2f8903eaae..0000000000
--- a/src/mainboard/thomson/ip1000/devicetree.cb
+++ /dev/null
@@ -1,68 +0,0 @@
-chip northbridge/intel/i82830		# Northbridge
-	device cpu_cluster 0 on		# APIC cluster
-		chip cpu/intel/socket_mFCBGA479	# Low Voltage PIII Micro-FCBGA Socket 479
-			device lapic 0 on end		# APIC
-		end
-	end
-
-	device domain 0 on		# PCI domain
-		device pci 0.0 on end		# Host bridge
-		device pci 2.0 on end		# VGA (Intel 82830 CGC)
-		chip southbridge/intel/i82801dx	# Southbridge
-			register "pirqa_routing" = "0x05"
-			register "pirqb_routing" = "0x06"
-			register "pirqc_routing" = "0x07"
-			register "pirqd_routing" = "0x09"
-			register "pirqe_routing" = "0x0a"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x0b"
-
-			register "ide0_enable" = "1"
-			register "ide1_enable" = "1"
-
-			device pci 1d.0 on end		# USB UHCI Controller #1
-			device pci 1d.1 on end		# USB UHCI Controller #2
-			device pci 1d.2 on end		# USB UHCI Controller #3
-			device pci 1d.7 on end		# USB2 EHCI Controller
-			device pci 1e.0 on end		# PCI bridge
-			device pci 1f.0 on		# ISA/LPC bridge
-				chip superio/smsc/smscsuperio	# Super I/O
-					device pnp 2e.0 off		# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.3 on		# Parallel port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-						drq 0x74 = 4
-					end
-					device pnp 2e.4 on		# Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.5 on		# Com2 / IR
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.7 on		# PS/2 keyboard/mouse
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1		# Keyboard interrupt
-						irq 0x72 = 12		# Mouse interrupt
-					end
-					device pnp 2e.9 off end	# Game port
-					device pnp 2e.a on		# PME
-						io 0x60 = 0x800
-					end
-					device pnp 2e.b off end	# MPU-401
-				end
-			end
-			device pci 1f.1 on end		# IDE
-			device pci 1f.3 on end		# SMBus
-			device pci 1f.5 on end		# AC'97 audio
-			device pci 1f.6 off end		# AC'97 modem
-		end
-	end
-end
diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c
deleted file mode 100644
index b4bf30e1ed..0000000000
--- a/src/mainboard/thomson/ip1000/gpio.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-
-#define PME_DEV			PNP_DEV(0x2e, 0x0a)
-#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
-#define ICH_IO_BASE_ADDR	0x00000500 /* GPIO base address register */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-	pci_devfn_t dev;
-	uint16_t port;
-	uint32_t set_gpio;
-
-	/* Southbridge GPIOs. */
-	/* Set the LPC device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-	/* Set the value for GPIO base address register and enable GPIO. */
-	pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));
-	pci_write_config8(dev, GPIO_CNTL, 0x10);
-
-	/* Set GPIO23 to high, this enables the LAN controller. */
-	udelay(10);
-	set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
-	set_gpio |= 1 << 23;
-	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
-
-	/* Disable AC97 Modem */
-	pci_write_config8(dev, 0xf2, 0x40);
-
-	/* Super I/O GPIOs. */
-	dev = PME_DEV;
-	port = dev >> 8;
-
-	/* Enter the configuration state. */
-	outb(0x55, port);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
-	pnp_set_enable(dev, 1);
-
-	/* GP21 - LED_RED */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2c);
-
-	/* GP30 - FAN2_TACH */
-	outl(0x05, PME_IO_BASE_ADDR + 0x33);
-
-	/* GP31 - FAN1_TACH */
-	outl(0x05, PME_IO_BASE_ADDR + 0x34);
-
-	/* GP32 - FAN2_CTRL */
-	outl(0x04, PME_IO_BASE_ADDR + 0x35);
-
-	/* GP33 - FAN1_CTRL */
-	outl(0x04, PME_IO_BASE_ADDR + 0x36);
-
-	/* GP34 - AUD_MUTE_OUT_R */
-	outl(0x00, PME_IO_BASE_ADDR + 0x37);
-
-	/* GP36 - KBRST */
-	outl(0x00, PME_IO_BASE_ADDR + 0x39);
-
-	/* GP37 - A20GATE */
-	outl(0x00, PME_IO_BASE_ADDR + 0x3a);
-
-	/* GP42 - GPIO_PME_OUT */
-	outl(0x00, PME_IO_BASE_ADDR + 0x3d);
-
-	/* GP50 - SER2_RI */
-	outl(0x05, PME_IO_BASE_ADDR + 0x3f);
-
-	/* GP51 - SER2_DCD */
-	outl(0x05, PME_IO_BASE_ADDR + 0x40);
-
-	/* GP52 - SER2_RX */
-	outl(0x05, PME_IO_BASE_ADDR + 0x41);
-
-	/* GP53 - SER2_TX */
-	outl(0x04, PME_IO_BASE_ADDR + 0x42);
-
-	/* GP55 - SER2_RTS */
-	outl(0x04, PME_IO_BASE_ADDR + 0x44);
-
-	/* GP56 - SER2_CTS */
-	outl(0x05, PME_IO_BASE_ADDR + 0x45);
-
-	/* GP57 - SER2_DTR */
-	outl(0x04, PME_IO_BASE_ADDR + 0x46);
-
-	/* GP60 - LED_GREEN */
-	outl(0x01, PME_IO_BASE_ADDR + 0x47);
-
-	/* GP61 - LED_YELLOW */
-	outl(0x01, PME_IO_BASE_ADDR + 0x48);
-
-	/* GP3 */
-	outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
-
-	/* GP4 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x4e);
-
-	/* FAN1 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x56);
-
-	/* FAN2 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x57);
-
-	/* Fan Control */
-	outl(0x50, PME_IO_BASE_ADDR + 0x58);
-
-	/* Fan1 Tachometer */
-	outl(0xff, PME_IO_BASE_ADDR + 0x59);
-
-	/* Fan2 Tachometer */
-	outl(0xff, PME_IO_BASE_ADDR + 0x5a);
-
-	/* LED1 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5d);
-
-	/* LED2 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5e);
-
-	/* Keyboard Scan Code */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5f);
-
-	/* Exit the configuration state. */
-	outb(0xaa, port);
-}
diff --git a/src/mainboard/thomson/ip1000/irq_tables.c b/src/mainboard/thomson/ip1000/irq_tables.c
deleted file mode 100644
index e99adfcbc5..0000000000
--- a/src/mainboard/thomson/ip1000/irq_tables.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,    /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
-	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
-	0,		 /* IRQs devoted exclusively to PCI usage */
-	0x8086,		 /* Vendor */
-	0x24c0,		 /* Device */
-	0,		 /* Miniport data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x07,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x02 << 3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */
-		{0x00,(0x1d << 3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */
-		{0x00,(0x1f << 3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */
-		{0x01,(0x08 << 3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */
-		{0x01,(0x00 << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */
-		{0x01,(0x01 << 3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */
-		{0x01,(0x02 << 3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c
deleted file mode 100644
index bdcc1fa00b..0000000000
--- a/src/mainboard/thomson/ip1000/mainboard.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
- * Copyright (C) 2010 Stefan Reinauer <stepan@openbios.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <delay.h>
-#include <drivers/intel/gma/int15.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-
-// setting the bit disables the led.
-#define PARPORT_GPIO_LED_GREEN	(1 << 0)
-#define PARPORT_GPIO_LED_ORANGE	(1 << 1)
-#define PARPORT_GPIO_LED_RED	(1 << 2)
-#define PARPORT_GPIO_IR_PORT	(1 << 6)
-
-static u8 get_parport_gpio(void)
-{
-	return inb(0x378);
-}
-
-static void set_parport_gpio(u8 gpios)
-{
-	outb(gpios, 0x378);
-}
-
-static void parport_gpios(void)
-{
-	u8 pp_gpios = get_parport_gpio();
-
-	/* disable red led */
-	pp_gpios |= PARPORT_GPIO_LED_RED;
-	set_parport_gpio(pp_gpios);
-
-	pp_gpios = get_parport_gpio();
-
-	printk(BIOS_DEBUG, "IP1000 GPIOs:\n");
-	printk(BIOS_DEBUG, "  GPIO mask:  %02x\n", pp_gpios);
-	printk(BIOS_DEBUG, "  green led:  %s\n",
-			(pp_gpios & PARPORT_GPIO_LED_GREEN) ? "off" : "on");
-	printk(BIOS_DEBUG, "  orange led: %s\n",
-			(pp_gpios & PARPORT_GPIO_LED_ORANGE) ? "off" : "on");
-	printk(BIOS_DEBUG, "  red led:    %s\n",
-			(pp_gpios & PARPORT_GPIO_LED_RED) ? "off" : "on");
-	printk(BIOS_DEBUG, "  IR port:    %s\n",
-			(pp_gpios & PARPORT_GPIO_IR_PORT) ? "off" : "on");
-}
-
-static void flash_gpios(void)
-{
-	u8 manufacturer_id = read8((u8 *)0xffbc0000);
-	u8 device_id = read8((u8 *)0xffbc0001);
-
-	if ((manufacturer_id == 0x20) &&
-		((device_id == 0x2c) || (device_id == 0x2d))) {
-		printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n",
-				(device_id == 0x2c)?'4':'8');
-		u8 fgpi = read8((u8 *)0xffbc0100);
-		printk(BIOS_DEBUG, "  FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n",
-			(fgpi & (1 << 0)) ? 'X' : ' ',
-			(fgpi & (1 << 1)) ? 'X' : ' ',
-			(fgpi & (1 << 2)) ? 'X' : ' ',
-			(fgpi & (1 << 3)) ? 'X' : ' ',
-			(fgpi & (1 << 4)) ? 'X' : ' ');
-	} else {
-		printk(BIOS_DEBUG, "No ST M50FW040/M50FW080 flash, don't read FGPI.\n");
-	}
-}
-
-static void mainboard_init(device_t dev)
-{
-	parport_gpios();
-	flash_gpios();
-}
-
-static void mainboard_enable(device_t dev)
-{
-	dev->ops->init = mainboard_init;
-	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c
deleted file mode 100644
index 9ad12257c3..0000000000
--- a/src/mainboard/thomson/ip1000/romstage.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <lib.h>
-#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include <northbridge/intel/i82830/raminit.h>
-#include "northbridge/intel/i82830/memory_initialized.c"
-#include <southbridge/intel/i82801dx/i82801dx.h>
-#include "southbridge/intel/i82801dx/reset.c"
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include "spd_table.h"
-#include "gpio.c"
-#include "southbridge/intel/i82801dx/tco_timer.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
-/**
- * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
- * values have to be set manually, the SO-DIMM socket is located in
- * socket0 (0x50/DIMM0), and the onboard memory is located in socket1
- * (0x51/DIMM1).
- */
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	int i;
-
-	if (device == DIMM0) {
-		return smbus_read_byte(device, address);
-	} else if (device == DIMM1) {
-		for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
-			if (spd_table[i].address == address)
-				return spd_table[i].data;
-		}
-		return 0xFF; /* Return 0xFF when address is not found. */
-	} else {
-		return 0xFF; /* Return 0xFF on any failures. */
-	}
-}
-
-#include "northbridge/intel/i82830/raminit.c"
-
-/**
- * Setup mainboard specific registers pre raminit.
- */
-static void mb_early_setup(void)
-{
-	/* - Hub Interface to PCI Bridge Registers - */
-	/* 12-Clock Retry Enable */
-	pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
-	/* Master Latency Timer Count */
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
-	/* I/O Address Base */
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);
-
-	/* - LPC Interface Bridge Registers - */
-	/* Delayed Transaction Enable */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
-	/* Disable the TCO Timer system reboot feature */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
-	/* CPU Frequency Strap */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
-	/* ACPI base address and enable Resource Indicator */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
-	/* Enable the SMBUS */
-	enable_smbus();
-	/*  ACPI Enable */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
-	if (bist == 0) {
-		if (memory_initialized())
-			hard_reset();
-	}
-
-	/* Set southbridge and superio gpios */
-	mb_gpio_init();
-
-	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	/* Halt if there was a built in self test failure. */
-	report_bist_failure(bist);
-
-	/* disable TCO timers */
-	i82801dx_halt_tco_timer();
-
-	/* Setup mainboard specific registers */
-	mb_early_setup();
-
-	/* Initialize memory */
-	sdram_initialize();
-}
diff --git a/src/mainboard/thomson/ip1000/smihandler.c b/src/mainboard/thomson/ip1000/smihandler.c
deleted file mode 100644
index a8a7aca9f1..0000000000
--- a/src/mainboard/thomson/ip1000/smihandler.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-
-int mainboard_io_trap_handler(int smif)
-{
-	printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");
-	return 1;
-}
diff --git a/src/mainboard/thomson/ip1000/spd_table.h b/src/mainboard/thomson/ip1000/spd_table.h
deleted file mode 100644
index 1de05edce1..0000000000
--- a/src/mainboard/thomson/ip1000/spd_table.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <spd.h>
-
-#if IS_ENABLED(CONFIG_ONBOARD_MEMORY_64MB)
-
-#define DENSITY 0x10
-
-#elif IS_ENABLED(CONFIG_ONBOARD_MEMORY_128MB)
-
-#define DENSITY 0x20
-
-#endif
-
-struct spd_entry {
-	unsigned int address;
-	unsigned int data;
-};
-
-/*
- * The onboard 64MB PC133 memory does not have an SPD EEPROM so the values
- * have to be set manually, the onboard memory is located in socket1 (0x51).
- */
-const struct spd_entry spd_table [] = {
-	{SPD_MEMORY_TYPE,                     0x04}, /* (Fundamental) memory type */
-	{SPD_NUM_COLUMNS,                     0x09}, /* Number of column address bits */
-	{SPD_NUM_DIMM_BANKS,                  0x01}, /* Number of module rows (banks) */
-	{SPD_MODULE_DATA_WIDTH_LSB,           0x40}, /* Module data width (LSB) */
-	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX,       0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
-	{SPD_ACCESS_TIME_FROM_CLOCK,          0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
-	{SPD_DENSITY_OF_EACH_ROW_ON_MODULE,   DENSITY}, /* Density of each row on module */
-};
diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig
deleted file mode 100644
index d0bee8f9eb..0000000000
--- a/src/northbridge/intel/i82830/Kconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-config NORTHBRIDGE_INTEL_I82830
-	bool
-	select NO_MMCONF_SUPPORT
-	select HAVE_DEBUG_RAM_SETUP
-	select LATE_CBMEM_INIT
-	select UDELAY_IO
-
-choice
-	prompt "Onboard graphics"
-	default I830_VIDEO_MB_8MB
-	depends on NORTHBRIDGE_INTEL_I82830
-
-config I830_VIDEO_MB_OFF
-	bool "Disabled, 0KB"
-config I830_VIDEO_MB_512KB
-	bool "Enabled, 512KB"
-config I830_VIDEO_MB_1MB
-	bool "Enabled, 1MB"
-config I830_VIDEO_MB_8MB
-	bool "Enabled, 8MB"
-
-endchoice
-
-config VIDEO_MB
-	int
-	default 0   if I830_VIDEO_MB_OFF
-	default 512 if I830_VIDEO_MB_512KB
-	default 1   if I830_VIDEO_MB_1MB
-	default 8   if I830_VIDEO_MB_8MB
-	depends on NORTHBRIDGE_INTEL_I82830
diff --git a/src/northbridge/intel/i82830/Makefile.inc b/src/northbridge/intel/i82830/Makefile.inc
deleted file mode 100644
index ebbae8111d..0000000000
--- a/src/northbridge/intel/i82830/Makefile.inc
+++ /dev/null
@@ -1,8 +0,0 @@
-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I82830),y)
-
-ramstage-y += northbridge.c
-ramstage-y += vga.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-endif
diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h
deleted file mode 100644
index a4b0a86c89..0000000000
--- a/src/northbridge/intel/i82830/i82830.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef NORTHBRIDGE_INTEL_I82830_I82830_H
-#define NORTHBRIDGE_INTEL_I82830_I82830_H
-
-#define RRBAR   0x48 /* Register Range Base Address (0x00000000) */
-#define GCC0    0x50 /* GMCH Control #0 (0xa072) */
-#define GCC1    0x52 /* GMCH Control #1 (0x0000) */
-#define FDHC    0x58 /* Fixed DRAM Hole Control (0x00) */
-#define PAM0    0x59 /* Programmable Attribute Map #0 (0x00) */
-#define PAM1    0x5a /* Programmable Attribute Map #1 (0x00) */
-#define PAM2    0x5b /* Programmable Attribute Map #2 (0x00) */
-#define PAM3    0x5c /* Programmable Attribute Map #3 (0x00) */
-#define PAM4    0x5d /* Programmable Attribute Map #4 (0x00) */
-#define PAM5    0x5e /* Programmable Attribute Map #5 (0x00) */
-#define PAM6    0x5f /* Programmable Attribute Map #6 (0x00) */
-#define DRB     0x60 /* DRAM Row Boundary #0 (0x00) */
-#define DRB1    0x61 /* DRAM Row Boundary #1 (0x00) */
-#define DRB2    0x62 /* DRAM Row Boundary #2 (0x00) */
-#define DRB3    0x63 /* DRAM Row Boundary #3 (0x00) */
-#define DRA     0x70 /* DRAM Row Attribute #0 (0xff) */
-#define DRA1    0x71 /* DRAM Row Attribute #1 (0xff) */
-#define DRT     0x78 /* DRAM Timing (0x00000010) */
-#define DRC     0x7c /* DRAM Controller Mode #0 (0x00000000) */
-#define DRC1    0x7d /* DRAM Controller Mode #1 (0x00000000) */
-#define DRC2    0x7e /* DRAM Controller Mode #2 (0x00000000) */
-#define DRC3    0x7f /* DRAM Controller Mode #3 (0x00000000) */
-#define DTC     0x8c /* DRAM Throttling Control (0x00000000) */
-#define SMRAM   0x90 /* System Management RAM Control (0x02) */
-#define ESMRAMC 0x91 /* Extended System Management RAM Control Reg. (0x38) */
-#define ERRSTS  0x92 /* Error Status (0x0000) */
-#define ERRCMD  0x94 /* Error Command (0x0000) */
-#define BUFF_SC 0xec /* System Memory Buffer Strength Control (0x00000000) */
-#define APBASE  0x10 /* Aperture Base Configuration (0x00000008) */
-#define APSIZE  0xb4 /* Aperture Size (0x00) */
-#define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */
-
-#endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */
diff --git a/src/northbridge/intel/i82830/memory_initialized.c b/src/northbridge/intel/i82830/memory_initialized.c
deleted file mode 100644
index 7ccc1a69c2..0000000000
--- a/src/northbridge/intel/i82830/memory_initialized.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include "i82830.h"
-#define NB_DEV PCI_DEV(0, 0, 0)
-
-static inline int memory_initialized(void)
-{
-	u32 drc;
-	drc = pci_read_config32(NB_DEV, DRC);
-	return (drc & (1<<29));
-}
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
deleted file mode 100644
index ce9a3fbe0b..0000000000
--- a/src/northbridge/intel/i82830/northbridge.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cbmem.h>
-#include <cpu/cpu.h>
-#include <stdlib.h>
-#include <string.h>
-#include "i82830.h"
-
-static void northbridge_init(device_t dev)
-{
-	printk(BIOS_SPEW, "Northbridge init\n");
-}
-
-static struct device_operations northbridge_operations = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = northbridge_init,
-	.enable = 0,
-	.ops_pci = 0,
-};
-
-static const struct pci_driver northbridge_driver __pci_driver = {
-	.ops = &northbridge_operations,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x3575,
-};
-
-static void pci_domain_set_resources(device_t dev)
-{
-	device_t mc_dev;
-	int igd_memory = 0;
-	uint64_t uma_memory_base = 0, uma_memory_size = 0;
-
-	mc_dev = dev->link_list->children;
-	if (!mc_dev)
-		return;
-
-	unsigned long tomk, tomk_stolen;
-	int idx;
-
-	if (CONFIG_VIDEO_MB == 512) {
-		igd_memory = (CONFIG_VIDEO_MB);
-		printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
-	} else {
-		igd_memory = (CONFIG_VIDEO_MB * 1024);
-		printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
-	}
-
-	/* Get the value of the highest DRB. This tells the end of
-	 * the physical memory. The units are ticks of 32MB
-	 * i.e. 1 means 32MB.
-	 */
-	tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
-	tomk_stolen = tomk - igd_memory;
-
-	/* For reserving UMA memory in the memory map */
-	uma_memory_base = tomk_stolen * 1024ULL;
-	uma_memory_size = igd_memory * 1024ULL;
-	printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk_stolen);
-
-	/* Report the memory regions. */
-	idx = 10;
-	ram_resource(dev, idx++, 0, 640);
-	ram_resource(dev, idx++, 768, tomk - 768);
-	uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10);
-
-	assign_resources(dev->link_list);
-
-	set_late_cbmem_top(tomk_stolen * 1024);
-}
-
-static struct device_operations pci_domain_ops = {
-	.read_resources		= pci_domain_read_resources,
-	.set_resources		= pci_domain_set_resources,
-	.enable_resources	= NULL,
-	.init			= NULL,
-	.scan_bus		= pci_domain_scan_bus,
-	.ops_pci_bus	= pci_bus_default_ops,
-};
-
-static void cpu_bus_init(device_t dev)
-{
-	initialize_cpus(dev->link_list);
-}
-
-static struct device_operations cpu_bus_ops = {
-	.read_resources		= DEVICE_NOOP,
-	.set_resources		= DEVICE_NOOP,
-	.enable_resources	= DEVICE_NOOP,
-	.init			= cpu_bus_init,
-	.scan_bus		= 0,
-};
-
-static void enable_dev(struct device *dev)
-{
-	struct device_path;
-
-	/* Set the operations if it is a special bus type. */
-	if (dev->path.type == DEVICE_PATH_DOMAIN) {
-		dev->ops = &pci_domain_ops;
-	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
-		dev->ops = &cpu_bus_ops;
-	}
-}
-
-struct chip_operations northbridge_intel_i82830_ops = {
-	CHIP_NAME("Intel 82830 Northbridge")
-	.enable_dev = enable_dev,
-};
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
deleted file mode 100644
index e0f2c6e476..0000000000
--- a/src/northbridge/intel/i82830/raminit.c
+++ /dev/null
@@ -1,508 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <spd.h>
-#include <delay.h>
-#include "lib/debug.c"
-#include "i82830.h"
-
-/*-----------------------------------------------------------------------------
-Macros and definitions.
------------------------------------------------------------------------------*/
-
-/* Debugging macros. */
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
-#define PRINTK_DEBUG(x...)	printk(BIOS_DEBUG, x)
-#define DUMPNORTH()		dump_pci_device(PCI_DEV(0, 0, 0))
-#else
-#define PRINTK_DEBUG(x...)
-#define DUMPNORTH()
-#endif
-
-/* DRC[10:8] - Refresh Mode Select (RMS).
- * 0x0 for Refresh Disabled (Self Refresh)
- * 0x1 for Refresh interval 15.6 us for 133MHz
- * 0x2 for Refresh interval 7.8 us for 133MHz
- * 0x7 for Refresh interval 128 Clocks. (Fast Refresh Mode)
- */
-#define RAM_COMMAND_REFRESH		0x1
-
-/* DRC[6:4] - SDRAM Mode Select (SMS). */
-#define RAM_COMMAND_SELF_REFRESH	0x0
-#define RAM_COMMAND_NOP			0x1
-#define RAM_COMMAND_PRECHARGE		0x2
-#define RAM_COMMAND_MRS			0x3
-#define RAM_COMMAND_CBR			0x6
-#define RAM_COMMAND_NORMAL		0x7
-
-/* DRC[29] - Initialization Complete (IC). */
-#define RAM_COMMAND_IC			0x1
-
-/*-----------------------------------------------------------------------------
-DIMM-initialization functions.
------------------------------------------------------------------------------*/
-
-static void do_ram_command(u32 command)
-{
-	u32 reg32;
-
-	/* Configure the RAM command. */
-	reg32 = pci_read_config32(NORTHBRIDGE, DRC);
-	/* Clear bits 29, 10-8, 6-4. */
-	reg32 &= 0xdffff88f;
-	reg32 |= command << 4;
-	PRINTK_DEBUG("  Sending RAM command 0x%08x", reg32);
-	pci_write_config32(NORTHBRIDGE, DRC, reg32);
-}
-
-static void ram_read32(u8 dimm_start, u32 offset)
-{
-	u32 reg32, base_addr = 32 * 1024 * 1024 * dimm_start;
-	if (offset == 0x55aa55aa) {
-		reg32 = read32((u32 *)base_addr);
-		PRINTK_DEBUG("  Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
-		PRINTK_DEBUG("  Writing RAM at 0x%08x <= 0x%08x\n", base_addr, offset);
-		write32((u32 *)base_addr, offset);
-		reg32 = read32((u32 *)base_addr);
-		PRINTK_DEBUG("  Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
-	} else {
-		PRINTK_DEBUG(" to 0x%08x\n", base_addr + offset);
-		read32((u32 *)(base_addr + offset));
-	}
-}
-
-static void initialize_dimm_rows(void)
-{
-	int i, row;
-	u8 dimm_start, dimm_end;
-	unsigned device;
-
-	dimm_start = 0;
-
-	for (row = 0; row < (DIMM_SOCKETS * 2); row++) {
-
-		switch (row) {
-			case 0:
-				device = DIMM0;
-				break;
-			case 1:
-				device = DIMM0;
-				break;
-			case 2:
-				device = DIMM0 + 1;
-				break;
-			case 3:
-				device = DIMM0 + 1;
-				break;
-		}
-
-		dimm_end = pci_read_config8(NORTHBRIDGE, DRB + row);
-
-		if (dimm_end > dimm_start) {
-			printk(BIOS_DEBUG, "Initializing SDRAM Row %u\n", row);
-
-			/* NOP command */
-			PRINTK_DEBUG(" NOP\n");
-			do_ram_command(RAM_COMMAND_NOP);
-			ram_read32(dimm_start, 0);
-			udelay(200);
-
-			/* Pre-charge all banks (at least 200 us after NOP) */
-			PRINTK_DEBUG(" Pre-charging all banks\n");
-			do_ram_command(RAM_COMMAND_PRECHARGE);
-			ram_read32(dimm_start, 0);
-			udelay(1);
-
-			/* 8 CBR refreshes (Auto Refresh) */
-			PRINTK_DEBUG(" 8 CBR refreshes\n");
-			for (i = 0; i < 8; i++) {
-				do_ram_command(RAM_COMMAND_CBR);
-				ram_read32(dimm_start, 0);
-				udelay(1);
-			}
-
-			/* MRS command */
-			/* TODO: Set offset 0x1d0 according to DRT values */
-			PRINTK_DEBUG(" MRS\n");
-			do_ram_command(RAM_COMMAND_MRS);
-			ram_read32(dimm_start, 0x1d0);
-			udelay(2);
-
-			/* Set GMCH-M Mode Select bits back to NORMAL operation mode */
-			PRINTK_DEBUG(" Normal operation mode\n");
-			do_ram_command(RAM_COMMAND_NORMAL);
-			ram_read32(dimm_start, 0);
-			udelay(1);
-
-			/* Perform a dummy memory read/write cycle */
-			PRINTK_DEBUG(" Performing dummy read/write\n");
-			ram_read32(dimm_start, 0x55aa55aa);
-			udelay(1);
-		}
-		/* Set the start of the next DIMM. */
-		dimm_start = dimm_end;
-	}
-}
-
-/*-----------------------------------------------------------------------------
-DIMM-independent configuration functions.
------------------------------------------------------------------------------*/
-
-struct dimm_size {
-	unsigned int side1;
-	unsigned int side2;
-};
-
-static struct dimm_size spd_get_dimm_size(unsigned device)
-{
-	struct dimm_size sz;
-	int i, module_density, dimm_banks;
-	sz.side1 = 0;
-	module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
-	dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
-
-	/* Find the size of side1. */
-	/* Find the larger value. The larger value is always side1. */
-	for (i = 512; i >= 0; i >>= 1) {
-		if ((module_density & i) == i) {
-			sz.side1 = i;
-			break;
-		}
-	}
-
-	/* Set to 0 in case it's single sided. */
-	sz.side2 = 0;
-
-	/* Test if it's a dual-sided DIMM. */
-	if (dimm_banks > 1) {
-		/* Test to see if there's a second value, if so it's asymmetrical. */
-		if (module_density != i) {
-			/* Find the second value, picking up where we left off. */
-			/* i >>= 1 done initially to make sure we don't get the same value again. */
-			for (i >>= 1; i >= 0; i >>= 1) {
-				if (module_density == (sz.side1 | i)) {
-					sz.side2 = i;
-					break;
-				}
-			}
-			/* If not, it's symmetrical */
-		} else {
-			sz.side2 = sz.side1;
-		}
-	}
-
-	/* SPD byte 31 is the memory size divided by 4 so we
-	 * need to multiply by 4 to get the total size.
-	 */
-	sz.side1 *= 4;
-	sz.side2 *= 4;
-	return sz;
-}
-
-static void set_dram_row_boundaries(void)
-{
-	int i, value, drb1, drb2;
-
-	for (i = 0; i < DIMM_SOCKETS; i++) {
-		struct dimm_size sz;
-		unsigned device;
-		device = DIMM0 + i;
-		drb1 = 0;
-		drb2 = 0;
-
-		/* First check if a DIMM is actually present. */
-		if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
-			printk(BIOS_DEBUG, "Found DIMM in slot %u\n", i);
-			sz = spd_get_dimm_size(device);
-			printk(BIOS_DEBUG, " DIMM is %uMB on side 1\n", sz.side1);
-			printk(BIOS_DEBUG, " DIMM is %uMB on side 2\n", sz.side2);
-
-			/* - Memory compatibility checks - */
-
-			/* Test for PC133 (i82830 only supports PC133) */
-			/* PC133 SPD9 - cycle time is always 75 */
-			if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) {
-				printk(BIOS_ERR, "SPD9 DIMM Is Not PC133 Compatable\n");
-				die("HALT\n");
-			}
-			/* PC133 SPD10 - access time is always 54 */
-			if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) {
-				printk(BIOS_ERR, "SPD10 DIMM Is Not PC133 Compatable\n");
-				die("HALT\n");
-			}
-
-			/* The i82830 only supports a symmetrical dual-sided dimms
-			 * and can't handle DIMMs smaller than 32MB per
-			 * side or larger than 256MB per side.
-			 */
-			if ((sz.side2 != 0) && (sz.side1 != sz.side2)) {
-				printk(BIOS_ERR, "This northbridge only supports\n");
-				printk(BIOS_ERR, "symmetrical dual-sided DIMMs\n");
-				printk(BIOS_ERR, "booting as a single-sided DIMM\n");
-				sz.side2 = 0;
-			}
-			if ((sz.side1 < 32)) {
-				printk(BIOS_ERR, "DIMMs smaller than 32MB per side\n");
-				printk(BIOS_ERR, "are not supported on this northbridge\n");
-				die("HALT\n");
-			}
-
-			if ((sz.side1 > 256)) {
-				printk(BIOS_ERR, "DIMMs larger than 256MB per side\n");
-				printk(BIOS_ERR, "are not supported on this northbridge\n");
-				die("HALT\n");
-			}
-			/* - End Memory compatibility checks - */
-
-			/* We need to divide size by 32 to set up the
-			 * DRB registers.
-			 */
-			if (sz.side1)
-				drb1 = sz.side1 / 32;
-			if (sz.side2)
-				drb2 = sz.side2 / 32;
-		} else {
-			printk(BIOS_DEBUG, "No DIMM found in slot %u\n", i);
-
-			/* If there's no DIMM in the slot, set value to 0. */
-			drb1 = 0;
-			drb2 = 0;
-		}
-		/* Set the value for DRAM Row Boundary Registers */
-		if (i == 0) {
-			pci_write_config8(NORTHBRIDGE, DRB, drb1);
-			pci_write_config8(NORTHBRIDGE, DRB + 1, drb1 + drb2);
-			PRINTK_DEBUG(" DRB 0x%02x has been set to 0x%02x\n", DRB, drb1);
-			PRINTK_DEBUG(" DRB1 0x%02x has been set to 0x%02x\n", DRB + 1, drb1 + drb2);
-		} else if (i == 1) {
-			value = pci_read_config8(NORTHBRIDGE, DRB + 1);
-			pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1);
-			pci_write_config8(NORTHBRIDGE, DRB + 3, value + drb1 + drb2);
-			PRINTK_DEBUG(" DRB2 0x%02x has been set to 0x%02x\n", DRB + 2, value + drb1);
-			PRINTK_DEBUG(" DRB3 0x%02x has been set to 0x%02x\n", DRB + 3, value + drb1 + drb2);
-
-			/* We need to set the highest DRB value to 0x64 and 0x65.
-			 * These are supposed to be "Reserved" but memory will
-			 * not initialize properly if we don't.
-			 */
-			value = pci_read_config8(NORTHBRIDGE, DRB + 3);
-			pci_write_config8(NORTHBRIDGE, DRB + 4, value);
-			pci_write_config8(NORTHBRIDGE, DRB + 5, value);
-		}
-	}
-}
-
-static void set_dram_row_attributes(void)
-{
-	int i, dra, col, width, value;
-
-	for (i = 0; i < DIMM_SOCKETS; i++) {
-		unsigned device;
-		device = DIMM0 + i;
-
-		/* First check if a DIMM is actually present. */
-		if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
-			PRINTK_DEBUG("Found DIMM in slot %u\n", i);
-
-			dra = 0x00;
-
-			/* columns */
-			col = spd_read_byte(device, SPD_NUM_COLUMNS);
-
-			/* data width */
-			width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
-
-			/* calculate page size in bits */
-			value = ((1 << col) * width);
-
-			/* convert to Kilobytes */
-			dra = ((value / 8) >> 10);
-
-			/* # of banks of DIMM (single or double sided) */
-			value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
-
-			if (value == 1) {
-				if (dra == 2) {
-					dra = 0xF0; /* 2KB */
-				} else if (dra == 4) {
-					dra = 0xF1; /* 4KB */
-				} else if (dra == 8) {
-					dra = 0xF2; /* 8KB */
-				} else if (dra == 16) {
-					dra = 0xF3; /* 16KB */
-				} else {
-					printk(BIOS_ERR, "Page size not supported\n");
-					die("HALT\n");
-				}
-			} else if (value == 2) {
-				if (dra == 2) {
-					dra = 0x00; /* 2KB */
-				} else if (dra == 4) {
-					dra = 0x11; /* 4KB */
-				} else if (dra == 8) {
-					dra = 0x22; /* 8KB */
-				} else if (dra == 16) {
-					dra = 0x33; /* 16KB */
-				} else {
-					printk(BIOS_ERR, "Page size not supported\n");
-					die("HALT\n");
-				}
-			} else {
-				printk(BIOS_ERR, "# of banks of DIMM not supported\n");
-				die("HALT\n");
-			}
-
-		} else {
-			PRINTK_DEBUG("No DIMM found in slot %u\n", i);
-
-			/* If there's no DIMM in the slot, set dra value to 0xFF. */
-			dra = 0xFF;
-		}
-
-		/* Set the value for DRAM Row Attribute Registers */
-		pci_write_config8(NORTHBRIDGE, DRA + i, dra);
-		PRINTK_DEBUG(" DRA 0x%02x has been set to 0x%02x\n", DRA + i, dra);
-	}
-}
-
-static void set_dram_timing(void)
-{
-	/* Set the value for DRAM Timing Register */
-	/* TODO: Configure the value according to SPD values. */
-	pci_write_config32(NORTHBRIDGE, DRT, 0x00000010);
-}
-
-static void set_dram_buffer_strength(void)
-{
-	/* TODO: This needs to be set according to the DRAM tech
-	 * (x8, x16, or x32). Argh, Intel provides no docs on this!
-	 * Currently, it needs to be pulled from the output of
-	 * lspci -xxx Rx92
-	 */
-
-	/* Set the value for System Memory Buffer Strength Control Registers */
-	pci_write_config32(NORTHBRIDGE, BUFF_SC, 0xFC9B491B);
-}
-
-/*-----------------------------------------------------------------------------
-Public interface.
------------------------------------------------------------------------------*/
-
-static void sdram_set_registers(void)
-{
-	printk(BIOS_DEBUG, "Setting initial SDRAM registers....\n");
-
-	/* Calculate the value for DRT DRAM Timing Register */
-	set_dram_timing();
-
-	/* Setup System Memory Buffer Strength Control Registers */
-	set_dram_buffer_strength();
-
-	/* Setup DRAM Row Boundary Registers */
-	set_dram_row_boundaries();
-
-	/* Setup DRAM Row Attribute Registers */
-	set_dram_row_attributes();
-
-	printk(BIOS_DEBUG, "Initial SDRAM registers have been set.\n");
-}
-
-static void northbridge_set_registers(void)
-{
-	u16 value;
-	int igd_memory = 0;
-
-	printk(BIOS_DEBUG, "Setting initial Northbridge registers....\n");
-
-	/* Set the value for Fixed DRAM Hole Control Register */
-	pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
-
-	/* Set the value for Programmable Attribute Map Registers
-	 * Ideally, this should be R/W for as many ranges as possible.
-	 */
-	pci_write_config8(NORTHBRIDGE, PAM0, 0x30);
-	pci_write_config8(NORTHBRIDGE, PAM1, 0x33);
-	pci_write_config8(NORTHBRIDGE, PAM2, 0x33);
-	pci_write_config8(NORTHBRIDGE, PAM3, 0x33);
-	pci_write_config8(NORTHBRIDGE, PAM4, 0x33);
-	pci_write_config8(NORTHBRIDGE, PAM5, 0x33);
-	pci_write_config8(NORTHBRIDGE, PAM6, 0x33);
-
-	/* Set the value for System Management RAM Control Register */
-	pci_write_config8(NORTHBRIDGE, SMRAM, 0x02);
-
-	/* Set the value for GMCH Control Register #0 */
-	pci_write_config16(NORTHBRIDGE, GCC0, 0xA072);
-
-	/* Set the value for Aperture Base Configuration Register */
-	pci_write_config32(NORTHBRIDGE, APBASE, 0x00000008);
-
-	/* Set the value for GMCH Control Register #1 */
-	switch (CONFIG_VIDEO_MB) {
-	case 512: /* 512K of memory */
-		igd_memory = 0x2;
-		break;
-	case 1: /* 1M of memory */
-		igd_memory = 0x3;
-		break;
-	case 8: /* 8M of memory */
-		igd_memory = 0x4;
-		break;
-	default: /* No memory */
-		pci_write_config16(NORTHBRIDGE, GCC1, 0x0002);
-		igd_memory = 0x0;
-	}
-
-	value = pci_read_config16(NORTHBRIDGE, GCC1);
-	value |= igd_memory << 4;
-	value |= 1; // 64MB aperture
-	pci_write_config16(NORTHBRIDGE, GCC1, value);
-
-	printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n");
-}
-
-static void sdram_initialize(void)
-{
-	u32 reg32;
-
-	/* Setup Initial SDRAM Registers */
-	sdram_set_registers();
-
-	/* Wait until power/voltages and clocks are stable (200us). */
-	udelay(200);
-
-	/* Initialize each row of memory one at a time */
-	initialize_dimm_rows();
-
-	/* Enable Refresh */
-	PRINTK_DEBUG("Enabling Refresh\n");
-	reg32 = pci_read_config32(NORTHBRIDGE, DRC);
-	reg32 |= (RAM_COMMAND_REFRESH << 8);
-	pci_write_config32(NORTHBRIDGE, DRC, reg32);
-
-	/* Set initialization complete */
-	PRINTK_DEBUG("Setting initialization complete\n");
-	reg32 = pci_read_config32(NORTHBRIDGE, DRC);
-	reg32 |= (RAM_COMMAND_IC << 29);
-	pci_write_config32(NORTHBRIDGE, DRC, reg32);
-
-	/* Setup Initial Northbridge Registers */
-	northbridge_set_registers();
-
-	PRINTK_DEBUG("Northbridge following SDRAM init:\n");
-	DUMPNORTH();
-}
diff --git a/src/northbridge/intel/i82830/raminit.h b/src/northbridge/intel/i82830/raminit.h
deleted file mode 100644
index 6b51db1349..0000000000
--- a/src/northbridge/intel/i82830/raminit.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef NORTHBRIDGE_INTEL_I82830_RAMINIT_H
-#define NORTHBRIDGE_INTEL_I82830_RAMINIT_H
-
-/* 82830 Northbridge PCI device */
-#define NORTHBRIDGE	PCI_DEV(0, 0, 0)
-
-/* The 82830 supports max. 2 dual-sided SO-DIMMs. */
-#define DIMM_SOCKETS	2
-
-#endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
deleted file mode 100644
index 569e62ec7b..0000000000
--- a/src/northbridge/intel/i82830/smihandler.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <compiler.h>
-#include <string.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/smm.h>
-#include <device/pci_def.h>
-#include "i82830.h"
-
-extern unsigned char *mbi;
-extern u32 mbi_len;
-
-// #define DEBUG_SMI_I82830
-
-/* If YABEL is enabled and it's not running at 0x00000000, we have to add some
- * offset to all our mbi object memory accesses
- */
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && !CONFIG_YABEL_DIRECTHW
-#define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION
-#else
-#define OBJ_OFFSET 0x00000
-#endif
-
-/* I830M */
-#define SMRAM		0x90
-#define   D_OPEN	(1 << 6)
-#define   D_CLS		(1 << 5)
-#define   D_LCK		(1 << 4)
-#define   G_SMRANE	(1 << 3)
-#define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
-
-
-typedef struct {
-	u32 mhid;
-	u32 function;
-	u32 retsts;
-	u32 rfu;
-} __packed banner_id_t;
-
-#define MSH_OK			0x0000
-#define MSH_OK_RESTART		0x0001
-#define MSH_FWH_ERR		0x00ff
-#define MSH_IF_BAD_ID		0x0100
-#define MSH_IF_BAD_FUNC		0x0101
-#define MSH_IF_MBI_CORRUPT	0x0102
-#define MSH_IF_BAD_HANDLE	0x0103
-#define MSH_ALRDY_ATCHED	0x0104
-#define MSH_NOT_ATCHED		0x0105
-#define MSH_IF			0x0106
-#define MSH_IF_INVADDR		0x0107
-#define MSH_IF_UKN_TYPE		0x0108
-#define MSH_IF_NOT_FOUND	0x0109
-#define MSH_IF_NO_KEY		0x010a
-#define MSH_IF_BUF_SIZE		0x010b
-#define MSH_IF_NOT_PENDING	0x010c
-
-#ifdef DEBUG_SMI_I82830
-static void
-dump(u8 * addr, u32 len)
-{
-	printk(BIOS_DEBUG, "\n%s(%p, %x):\n", __func__, addr, len);
-	while (len) {
-		unsigned int tmpCnt = len;
-		unsigned char x;
-		if (tmpCnt > 8)
-			tmpCnt = 8;
-		printk(BIOS_DEBUG, "\n%p: ", addr);
-		// print hex
-		while (tmpCnt--) {
-			x = *addr++;
-			printk(BIOS_DEBUG, "%02x ", x);
-		}
-		tmpCnt = len;
-		if (tmpCnt > 8)
-			tmpCnt = 8;
-		len -= tmpCnt;
-		//reset addr ptr to print ascii
-		addr = addr - tmpCnt;
-		// print ascii
-		while (tmpCnt--) {
-			x = *addr++;
-			if ((x < 32) || (x >= 127)) {
-				//non-printable char
-				x = '.';
-			}
-			printk(BIOS_DEBUG, "%c", x);
-		}
-	}
-	printk(BIOS_DEBUG, "\n");
-}
-#endif
-
-typedef struct {
-	banner_id_t banner;
-	u16 versionmajor;
-	u16 versionminor;
-	u32 smicombuffersize;
-} __packed version_t;
-
-typedef struct {
-	u16 header_id;
-	u16 attributes;
-	u16 size;
-	u8  name_len;
-	u8 reserved;
-	u32 type;
-	u32 header_ext;
-	u8 name[0];
-} __packed mbi_header_t;
-
-typedef struct {
-	banner_id_t banner;
-	u64 handle;
-	u32 objnum;
-	mbi_header_t header;
-} __packed obj_header_t;
-
-typedef struct {
-	banner_id_t banner;
-	u64 handle;
-	u32 objnum;
-	u32 start;
-	u32 numbytes;
-	u32 buflen;
-	u32 buffer;
-} __packed get_object_t;
-
-static void mbi_call(u8 subf, banner_id_t *banner_id)
-{
-#ifdef DEBUG_SMI_I82830
-	printk(BIOS_DEBUG, "MBI\n");
-	printk(BIOS_DEBUG, "|- sub function %x\n", subf);
-	printk(BIOS_DEBUG, "|- banner id @ %x\n", (u32)banner_id);
-	printk(BIOS_DEBUG, "|  |- mhid %x\n", banner_id->mhid);
-	printk(BIOS_DEBUG, "|  |- function %x\n", banner_id->function);
-	printk(BIOS_DEBUG, "|  |- return status %x\n", banner_id->retsts);
-	printk(BIOS_DEBUG, "|  |- rfu %x\n", banner_id->rfu);
-#endif
-
-	switch(banner_id->function) {
-	case 0x0001: {
-		version_t *version;
-		printk(BIOS_DEBUG, "|- MBI_QueryInterface\n");
-		version = (version_t *)banner_id;
-		version->banner.retsts = MSH_OK;
-		version->versionmajor = 1;
-		version->versionminor = 3;
-		version->smicombuffersize = 0x1000;
-		break;
-	}
-	case 0x0002:
-		printk(BIOS_DEBUG, "|- MBI_Attach\n");
-		printk(BIOS_DEBUG, "|  |- Not Implemented!\n");
-		break;
-	case 0x0003:
-		printk(BIOS_DEBUG, "|- MBI_Detach\n");
-		printk(BIOS_DEBUG, "|  |- Not Implemented!\n");
-		break;
-	case 0x0201: {
-		obj_header_t *obj_header = (obj_header_t *)banner_id;
-		mbi_header_t *mbi_header = NULL;
-		printk(BIOS_DEBUG, "|- MBI_GetObjectHeader\n");
-		printk(BIOS_DEBUG, "|  |- objnum = %d\n", obj_header->objnum);
-
-		int i, count = 0;
-		obj_header->banner.retsts = MSH_IF_NOT_FOUND;
-
-		for (i = 0; i < mbi_len;) {
-			int len;
-
-			if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {
-				i+=16;
-				continue;
-			}
-
-			mbi_header = (mbi_header_t *)&mbi[i];
-			len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
-
-			if (obj_header->objnum == count) {
-#ifdef DEBUG_SMI_I82830
-				if (mbi_header->name_len == 0xff) {
-					printk(BIOS_DEBUG, "|  |- corrupt.\n");
-					break;
-				}
-#endif
-				int headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
-#ifdef DEBUG_SMI_I82830
-				printk(BIOS_DEBUG, "|  |- headerlen = %d\n", headerlen);
-#endif
-				memcpy(&obj_header->header, mbi_header, headerlen);
-				obj_header->banner.retsts = MSH_OK;
-				printk(BIOS_DEBUG, "|     |- MBI module '");
-				int j;
-				for (j = 0; j < mbi_header->name_len && mbi_header->name[j]; j++)
-					printk(BIOS_DEBUG, "%c",  mbi_header->name[j]);
-				printk(BIOS_DEBUG, "' found.\n");
-#ifdef DEBUG_SMI_I82830
-				dump((u8 *)banner_id, sizeof(obj_header_t) + ALIGN(mbi_header->name_len, 16));
-#endif
-				break;
-			}
-			i += len;
-			count++;
-		}
-		if (obj_header->banner.retsts == MSH_IF_NOT_FOUND)
-			printk(BIOS_DEBUG, "|     |- MBI object #%d not found.\n", obj_header->objnum);
-		break;
-	}
-	case 0x0203: {
-		get_object_t *getobj = (get_object_t *)banner_id;
-		mbi_header_t *mbi_header = NULL;
-		printk(BIOS_DEBUG, "|- MBI_GetObject\n");
-#ifdef DEBUG_SMI_I82830
-		printk(BIOS_DEBUG, "|  |- handle = %016Lx\n", getobj->handle);
-#endif
-		printk(BIOS_DEBUG, "|  |- objnum = %d\n", getobj->objnum);
-		printk(BIOS_DEBUG, "|  |- start = %x\n", getobj->start);
-		printk(BIOS_DEBUG, "|  |- numbytes = %x\n", getobj->numbytes);
-		printk(BIOS_DEBUG, "|  |- buflen = %x\n", getobj->buflen);
-		printk(BIOS_DEBUG, "|  |- buffer = %x\n", getobj->buffer);
-
-		int i, count = 0;
-		getobj->banner.retsts = MSH_IF_NOT_FOUND;
-
-		for (i = 0; i< mbi_len;) {
-			int headerlen, objectlen;
-
-			if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {
-				i+=16;
-				continue;
-			}
-
-			mbi_header = (mbi_header_t *)&mbi[i];
-			headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
-			objectlen = ALIGN((mbi_header->size * 16), 16);
-
-			if (getobj->objnum == count) {
-				printk(BIOS_DEBUG, "|  |- len = %x\n", headerlen + objectlen);
-
-				memcpy((void *)(getobj->buffer + OBJ_OFFSET),
-						((char *)mbi_header) + headerlen, (objectlen > getobj->buflen) ? getobj->buflen : objectlen);
-
-				getobj->banner.retsts = MSH_OK;
-#ifdef DEBUG_SMI_I82830
-				dump((u8 *)banner_id, sizeof(*getobj));
-				dump((u8 *)getobj->buffer + OBJ_OFFSET, objectlen);
-#endif
-				break;
-			}
-			i += (headerlen + objectlen);
-			count++;
-		}
-		if (getobj->banner.retsts == MSH_IF_NOT_FOUND)
-			printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum);
-		break;
-	}
-	default:
-		printk(BIOS_DEBUG, "|- function %x\n", banner_id->function);
-		printk(BIOS_DEBUG, "|  |- Unknown Function!\n");
-		break;
-	}
-	printk(BIOS_DEBUG, "\n");
-	//dump(banner_id, 0x20);
-}
-
-#define SMI_IFC_SUCCESS		    1
-#define SMI_IFC_FAILURE_GENERIC     0
-#define SMI_IFC_FAILURE_INVALID     2
-#define SMI_IFC_FAILURE_CRITICAL    4
-#define SMI_IFC_FAILURE_NONCRITICAL 6
-
-#define PC10 	0x10
-#define PC11	0x11
-#define PC12	0x12
-#define PC13	0x13
-
-static void smi_interface_call(void)
-{
-  u8 *mmio = (u8 *)pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
-	// mmio &= 0xfff80000;
-	// printk(BIOS_DEBUG, "mmio=%x\n", mmio);
-	u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);
-
-	if (!(swsmi & 1))
-		return;
-
-	swsmi &= ~(1 << 0); // clear SMI toggle
-
-	switch ((swsmi>>1) & 0xf) {
-	case 0:
-		printk(BIOS_DEBUG, "Interface Function Presence Test.\n");
-		swsmi = 0;
-		swsmi &= ~(7 << 5); // Exit: Result
-		swsmi |= (SMI_IFC_SUCCESS << 5);
-		swsmi &= 0xff;
-		swsmi |= (PC13 << 8);
-		pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
-		// write magic
-		write32(mmio + 0x71428, 0x494e5443);
-		return;
-	case 4:
-		printk(BIOS_DEBUG, "Get BIOS Data.\n");
-		printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
-		break;
-	case 5:
-		printk(BIOS_DEBUG, "Call MBI Functions.\n");
-		mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + 0x71428) & 0x000fffff) + OBJ_OFFSET) );
-		// swsmi = 0x0000;
-		swsmi &= ~(7 << 5); // Exit: Result
-		swsmi |= (SMI_IFC_SUCCESS << 5);
-		pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
-		return;
-	case 6:
-		printk(BIOS_DEBUG, "System BIOS Callbacks.\n");
-		printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
-		break;
-	default:
-		printk(BIOS_DEBUG, "Unknown SMI interface call %04x\n", swsmi);
-		break;
-	}
-
-	swsmi &= ~(7 << 5); // Exit: Result
-	swsmi |= (SMI_IFC_FAILURE_CRITICAL << 7);
-	pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
-}
-
-/**
- * @brief read and clear ERRSTS
- * @return ERRSTS register
- */
-static u16 reset_err_status(void)
-{
-	u16 reg16;
-
-	reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), ERRSTS);
-	/* set status bits are cleared by writing 1 to them */
-	pci_write_config16(PCI_DEV(0, 0x00, 0), ERRSTS, reg16);
-
-	return reg16;
-}
-
-static void dump_err_status(u32 errsts)
-{
-	printk(BIOS_DEBUG, "ERRSTS: ");
-	if (errsts & (1 << 12)) printk(BIOS_DEBUG, "MBI ");
-	if (errsts & (1 <<  9)) printk(BIOS_DEBUG, "LCKF ");
-	if (errsts & (1 <<  8)) printk(BIOS_DEBUG, "DTF ");
-	if (errsts & (1 <<  5)) printk(BIOS_DEBUG, "UNSC ");
-	if (errsts & (1 <<  4)) printk(BIOS_DEBUG, "OOGF ");
-	if (errsts & (1 <<  3)) printk(BIOS_DEBUG, "IAAF ");
-	if (errsts & (1 <<  2)) printk(BIOS_DEBUG, "ITTEF ");
-	printk(BIOS_DEBUG, "\n");
-}
-
-void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
-{
-	u16 errsts;
-
-	/* We need to clear the SMI status registers, or we won't see what's
-	 * happening in the following calls.
-	 */
-	errsts = reset_err_status();
-	if (errsts & (1 << 12)) {
-		smi_interface_call();
-	} else {
-		if (errsts)
-			dump_err_status(errsts);
-	}
-
-}
diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c
deleted file mode 100644
index 20c9d0a3f6..0000000000
--- a/src/northbridge/intel/i82830/vga.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cbfs.h>
-#include <x86emu/x86emu.h>
-
-static void vga_init(device_t dev)
-{
-	printk(BIOS_INFO, "Starting Graphics Initialization\n");
-	size_t mbi_len;
-	void *mbi = cbfs_boot_map_with_leak("mbi.bin", CBFS_TYPE_MBI, &mbi_len);
-
-	if (mbi && mbi_len) {
-		/* The GDT or coreboot table is going to live here. But
-		 * a long time after we relocated the GNVS, so this is
-		 * not troublesome.
-		 */
-		*(u32 *)0x500 = (u32)mbi;
-		*(u32 *)0x504 = (u32)mbi_len;
-		outb(0xeb, 0xb2);
-	}
-
-	pci_dev_init(dev);
-	printk(BIOS_INFO, "Graphics Initialization Complete\n");
-
-	/* Enable TV-Out */
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
-#define PIPE_A_CRT	(1 << 0)
-#define PIPE_A_LFP	(1 << 1)
-#define PIPE_A_TV	(1 << 3)
-#define PIPE_B_CRT	(1 << 8)
-#define PIPE_B_TV	(1 << 10)
-	printk(BIOS_DEBUG, "Enabling TV-Out\n");
-	void runInt10(void);
-	X86_AX = 0x5f64;
-	X86_BX = 0x0001; // Set Display Device, force execution
-	X86_CX = PIPE_A_CRT | PIPE_A_TV;
-	// M.x86.R_CX = PIPE_B_TV;
-	runInt10();
-	switch (X86_AX) {
-	case 0x005f:
-		printk(BIOS_DEBUG, "... failed.\n");
-		break;
-	case 0x015f:
-		printk(BIOS_DEBUG, "... ok.\n");
-		break;
-	default:
-		printk(BIOS_DEBUG, "... not supported.\n");
-		break;
-	}
-#endif
-}
-
-static const struct device_operations vga_operations = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = vga_init,
-	.scan_bus         = 0,
-	.enable           = 0,
-	.ops_pci          = 0,
-};
-
-static const struct pci_driver vga_driver __pci_driver = {
-	.ops    = &vga_operations,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x3577,
-};