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authorHannah Williams <hannah.williams@intel.com>2017-12-13 12:44:26 -0800
committerAaron Durbin <adurbin@chromium.org>2018-02-05 18:53:16 +0000
commit1177bf516540b62e54cefdf346bb6e8a7c376642 (patch)
tree16816da12ba7ba556300e8a5599b0bb21f1a631c /src
parent8b40b675a8e45f748e7fbf2495a7f01684fa0401 (diff)
downloadcoreboot-1177bf516540b62e54cefdf346bb6e8a7c376642.tar.xz
soc/intel/common/block/pmc: Fix ACPI BAR and PCI_COMMAND in PMC config space
read_resources in common/block/pmc/pmc.c is corrupting the BAR at offset 0x20. pch_pmc_read_resources | pci_dev_read_resources | pci_get_resource Within pci_get_resource, the BAR is read and written back. Since read of ACPI BAR does not return the correct value, the subsequent write corrupts the BAR. Hence re-programming the BAR. Also, reading PMC STATUSCOMMAND register does not return bit 0 correctly in pci_dev_enable_resources. This causes IO SPACE ACCESS to get disabled. Hence making sure IO ACCESS gets enabled by setting dev->command TEST=Can boot to OS Without this change coreboot will be stuck at "Disabling ACPI via APMC:" Change-Id: I27062419d06127951ecbbb641835d06ca39ff435 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23230 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/Kconfig1
-rw-r--r--src/soc/intel/common/block/pmc/Kconfig7
-rw-r--r--src/soc/intel/common/block/pmc/pmc.c17
3 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index b7f2dc92c4..a9f49dbbfd 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -57,6 +57,7 @@ config CPU_SPECIFIC_OPTIONS
select PCIEX_LENGTH_256MB
select POSTCAR_CONSOLE
select POSTCAR_STAGE
+ select PMC_INVALID_READ_AFTER_WRITE
select REG_SCRIPT
select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
select RTC
diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig
index cfd12d8f3e..46f134e3b1 100644
--- a/src/soc/intel/common/block/pmc/Kconfig
+++ b/src/soc/intel/common/block/pmc/Kconfig
@@ -30,3 +30,10 @@ config POWER_STATE_PREVIOUS_AFTER_FAILURE
power
endchoice
+
+config PMC_INVALID_READ_AFTER_WRITE
+ bool
+ default n
+ help
+ Enable this for PMC devices where a read back of ACPI BAR and
+ IO access bit does not return the previously written value.
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index a3c5c4216c..f9563302df 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -65,6 +65,23 @@ static void pch_pmc_add_io_resources(struct device *dev,
cfg->abase_addr, cfg->abase_size,
IORESOURCE_IO | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED);
+ if (IS_ENABLED(CONFIG_PMC_INVALID_READ_AFTER_WRITE)) {
+ /*
+ * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've
+ * observed cases where the BAR reads back as 0, but the IO
+ * window is open. This also means that it will not respond
+ * to PCI probing.
+ */
+ pci_write_config16(dev, cfg->abase_offset, cfg->abase_addr);
+ /*
+ * In pci_dev_enable_resources, reading IO SPACE ACCESS bit in
+ * STATUSCOMMAND register does not read back the written
+ * value correctly, hence IO access gets disabled. This is
+ * seen in some PMC devices, hence this code makes sure
+ * IO access is available.
+ */
+ dev->command |= PCI_COMMAND_IO;
+ }
}
static void pch_pmc_read_resources(struct device *dev)