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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-01 18:33:39 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-20 10:30:49 +0200 |
| commit | 1222162d12eeecd266c7124b6978a5d21d51cc6e (patch) | |
| tree | 28c2974b349fc62b09938dd51c27d8df73443ef7 /src | |
| parent | bd23bd62b4ccb75d76209cbe1cd0e867b6d1017f (diff) | |
| download | coreboot-1222162d12eeecd266c7124b6978a5d21d51cc6e.tar.xz | |
mb/gigabyte/ga-g41m-es2l: Add timestamps in romstage
Change-Id: I93f43a0af41ae86f1b8ba33e28f3b9f060a5ab5e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 229f028d9a..b16f736be2 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -31,6 +31,7 @@ #include <arch/stages.h> #include <cbmem.h> #include <northbridge/intel/x4x/iomap.h> +#include <timestamp.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) @@ -135,6 +136,9 @@ void mainboard_romstage_entry(unsigned long bist) u8 boot_path = 0; u8 s3_resume; + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -160,7 +164,9 @@ void mainboard_romstage_entry(unsigned long bist) boot_path = BOOT_PATH_WARM_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); + timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); printk(BIOS_DEBUG, "Memory initialized\n"); |