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authorIonela Voinescu <ionela.voinescu@imgtec.com>2015-01-19 01:05:16 +0000
committerPatrick Georgi <pgeorgi@google.com>2015-04-14 12:07:52 +0200
commit1c0d0c01591f22e554fda82a34150f63a9e5b8fc (patch)
tree291dba8a3ea342067f15f9dc96b3978a526b8504 /src
parentb3f666b252a7057a49f24b239e7f6c4ffd4f3350 (diff)
downloadcoreboot-1c0d0c01591f22e554fda82a34150f63a9e5b8fc.tar.xz
pistachio: spi: use same clock edge for RX and TX
When using this mode data is received and transmitted on the same edge of the SPFI clock, which allows for higher frequencies of operation. In this mode the maximum supported frequency is 50Mhz. If this mode is not enabled the maximum supported frequency is 25Mhz. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; the SPFI hardware block is fed by the system clock (with a fixed freqency of 400 MHz). To achieve the SPFI frequency of 50MHz the internal divider of SPFI must be set to 64. To achieve a frequency of 25 Mhz the internal divider must be set to 32. A value of 64 = division by 8 A value of 32 = division by 16 BRANCH=none Change-Id: Ifd5f739b6157b99e4c1f92b5bb72615ee610ae6c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8b6cce616ec7926682d4eff096563acf1dfd6c65 Original-Change-Id: I337b6fcf462bcf6021ca77a8b1133cf49140ba76 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241425 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/imgtec/pistachio/spi.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c
index 5522f2408e..64d18a3ca0 100644
--- a/src/soc/imgtec/pistachio/spi.c
+++ b/src/soc/imgtec/pistachio/spi.c
@@ -222,6 +222,7 @@ static u32 control_reg_setup(struct spim_buffer *first,
/* Set up the transfer mode */
reg = spi_write_reg_field(reg, SPFI_TRNSFR_MODE_DQ, SPIM_CMD_MODE_0);
reg = spi_write_reg_field(reg, SPFI_TRNSFR_MODE, SPIM_DMODE_SINGLE);
+ reg = spi_write_reg_field(reg, SPIM_EDGE_TX_RX, 1);
if (second) {
/* Set TX bit if the 2nd transaction is 'send' */