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authorHung-Te Lin <hungte@chromium.org>2013-08-08 11:07:40 +0800
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 22:46:09 +0100
commit20316321fbf4cab423961f73df31795ec6dea670 (patch)
treee21d705295be0ecfdb0ab47048fb30ca7adeb227 /src
parente0cfad2b563a26365041dcf75fe7b8302fcab5a4 (diff)
downloadcoreboot-20316321fbf4cab423961f73df31795ec6dea670.tar.xz
armv7: Allow accessing ACTLR (Auxiliary Control Register)
The ACTLR provides implementation defined configuration and control options for the processor. Change-Id: I74df1ed7887eb3f16a1b8297db998ec2f8b18311 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65107 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4447 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
-rw-r--r--src/arch/armv7/include/arch/cpu.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/armv7/include/arch/cpu.h
index efd2dc9af9..2613025348 100644
--- a/src/arch/armv7/include/arch/cpu.h
+++ b/src/arch/armv7/include/arch/cpu.h
@@ -66,6 +66,20 @@ inline static uint32_t read_mpidr(void)
return value;
}
+/* read Auxiliary Control Register (ACTLR) */
+inline static uint32_t read_actlr(void)
+{
+ uint32_t val = 0;
+ asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r"(val));
+ return val;
+}
+
+/* write Auxiliary Control Register (ACTLR) */
+inline static void write_actlr(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (val));
+}
+
/* wait for interrupt. */
inline static void wfi(void)
{